Optical Communication Timing Synchronization via Round-Trip Delay

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Solution Overview

Problem

In optical communication systems, accurately controlling signal transmission and reception timing is crucial to avoid collisions and signal loss, especially in systems using TDMA, where existing methods do not adequately account for processing delays in master and slave devices.

Innovation Solution

A communication system with a control network for transmitting control signals and an optical network for data signals, where the master device calculates and adjusts for round-trip delay times to synchronize data transmission and reception between the master and slave devices, ensuring accurate timing through the use of TDMA control circuits and transmission/reception circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If TDMA is used to share optical fiber among multiple communication devices, then communication capacity increases, but signal collision and loss occur due to inaccurate timing synchronization

Engineering Contradiction:
Improvecommunication capacityVSAvoidsignal transmission reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the master device measures round-trip delay times to slave devices by transmitting control signals and receiving reflected signals with time stamps. The measured delay information is fed back to adjust transmission timing, enabling continuous optimization of synchronization accuracy and preventing signal collisions while maintaining high communication capacity

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary timing adjustment by calculating round-trip delay times before actual data transmission. The master device measures delay characteristics in advance and uses this information to pre-adjust transmission timing slots, ensuring that subsequent data transmissions are properly synchronized without collisions

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If timing control is simplified in optical communication, then device complexity decreases, but transmission and reception timing accuracy deteriorates

Engineering Contradiction:
Improvetiming control complexityVSAvoidtiming synchronization precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements a self-service timing synchronization mechanism where each slave device autonomously measures its own round-trip delay time with the master device using time-stamped control signals. Each device independently calculates and adjusts its transmission timing based on self-measured delay information, eliminating the need for complex centralized timing control while achieving high synchronization precision

Inventive Principle:
Principle #25Self-service

3Measurement precision

If round-trip delay time measurement is implemented, then timing synchronization accuracy improves, but device complexity increases due to additional control circuits

Engineering Contradiction:
Improvetiming synchronization precisionVSAvoidcontrol circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the timing measurement and control functions with existing data transmission and reception circuits. The same communication channels carry both data signals and control signals for delay measurement, and existing processors handle timing calculation and adjustment, avoiding the need for separate dedicated measurement hardware and reducing overall device complexity

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12199850B2Communication system, master device, slave device and communication method
Publication Date: 2025.01.14 MEGACHIPS
  • US12199850B2 patent drawing
  • US12199850B2 patent drawing
  • US12199850B2 patent drawing

AI summary

A master device transmits a first control signal including TS0(S) to a slave device and transmits a first data signal including TS0(M) to the master, the slave sets a point in time in the slave to T0(S) in time when the first control signal is received and transmits a second data signal including TS1(S) to the master, the master receives the second data signal and subtract TS1(S) from TS2(S) to calculate a round-trip delay time RTTs, and receives the first data signal and subtract TS0(M) from TS1(M) to calculate a round-trip delay time RTTm, the master transmits a data signal to the slave at a point in time that is obtained by TA−RTTm, and the slave puts the slave in a data receivable state at a point in time that is obtained by TA−RTTs.