Optical Transceiver Output Stabilization via MCU State Bit Forcing
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Solution Overview
Problem
Optical transceivers experience unstable output states due to an unstable CDR chip when there is no data input, affecting the estimation of the working condition.
Innovation Solution
A method that compares the signal quality monitor register value with a predetermined threshold, and when it's below the threshold, the microcontroller unit converts the state bit values of the CDR chip to either low or high logic levels to stabilize the output state, preventing toggling and maintaining a stable state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CDR chip operates without data input, then the optical transceiver can maintain readiness for data reception, but the output state becomes unstable due to continuous toggling of state flag bits
Solution Approach 1:
The patent introduces an intermediary mechanism (state bit monitoring and forcing logic) between the CDR chip's internal state flags and the optical transceiver's output display. When no data is input, the system detects the toggling state bits and forces them to stable values before they can affect the output, thus mediating the instability without preventing the CDR chip from remaining ready for data reception.
2Loss of information
If the state bit values are allowed to toggle naturally, then the CDR chip accurately reflects its operational state, but the optical transceiver output display becomes unstable and difficult to interpret
Solution Approach 1:
The patent extracts the unstable state bit information from the CDR chip and separates it from the final output display path. By detecting toggling state bits and forcing them to stable values independently, the system removes the harmful instability while preserving the CDR chip's accurate state reflection internally, preventing the unstable state from reaching the output display.
3Speed
If the CDR chip continuously monitors for data input, then it can quickly detect when data arrives, but the state flag bits continuously vary causing unstable output state
Solution Approach 1:
The patent applies preliminary action by proactively detecting and forcing stable values on state bit values before they can propagate to the output display. The system continuously monitors state bit values and pre-empts potential instability by forcing low logic level values when toggling is detected, ensuring the output state remains reliable while the CDR chip continues its rapid data arrival detection.
Data Source
AI summary
The invention relates to a method and algorithm for stabilizing the output state of an optical transceiver. The method includes comparing a signal quality monitor (SQM) register value with a predetermined threshold. If the SQM register value is less than or equal to the predetermined threshold, a microcontroller unit (MCU) reads and determines the rx_lol state bit value of a clock and data recovery (CDR) chip. If the rx_lol state bit value reaches a low logic level value at least 3 times, the MCU converts the state bit values of rx_lol and mod_nr into low logic level values, or else, convert the state bit values of rx_lol and mod_nr into high logic level values. If the SQM register value is greater than the predetermined threshold then the state bit values of rx_lol and mod_nr will be left unchanged. When there is no data input to the CDR chip, the method of the present invention will maintain rx_lol and mod_nr at high or low logic level values to stabilize the output state of the optical transceiver.