Optical TSV Optoelectronic Chip Stacking for III-V Silicon Coupling
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Solution Overview
Problem
Current silicon-based III-V compound semiconductor hybrid integration methods face challenges such as complex manufacturing processes, material wastage, lattice and thermal mismatch, alignment accuracy issues, and high costs, making it difficult to achieve efficient optical coupling and electrical interconnection in data centers and intelligent computing systems.
Innovation Solution
A heterogeneously integrated optoelectronic chip using optical through-substrate vias (TSVs) for 3D integration, which allows optical signals to travel through InP and Si substrates, enabling efficient optical coupling between III-V waveguide layers and SOI or SiN layers, and avoiding flip-chip bonding, while allowing electrical interconnection through front electrode layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-V/SOI bonding technology based on evanescent wave coupling is used, then optical coupling between III-V and Si waveguides is achieved, but the manufacturing process becomes complex and material wastage increases
Solution Approach 1:
The patent extracts the optical coupling function from the complex bonding interface and relocates it to the end-face of the III-V chip. By using free-space optical coupling at the chip end-face rather than through-substrate evanescent coupling, the manufacturing process is simplified while maintaining optical coupling efficiency.
Solution Approach 2:
The patent introduces an optical intermediary (free-space optical path) between the III-V chip and Si substrate to enable optical coupling without direct physical bonding. This intermediary approach avoids the complexity of evanescent wave coupling through bonded interfaces.
2Ease of operation
If flip chip bonding is used for end face coupling, then electrical interconnection is achieved, but alignment accuracy becomes difficult to achieve due to small mode field waveguides
Solution Approach 1:
The patent segments the optical and electrical interconnection functions into separate pathways. Optical coupling is achieved through free-space optical paths at the chip end-face, while electrical interconnection is achieved through separate electrical contacts, allowing each to be optimized independently without mutual interference.
Solution Approach 2:
The patent transitions from planar waveguide coupling to three-dimensional free-space optical coupling. By using vertical optical paths at the chip end-face rather than lateral waveguide coupling, the system achieves better alignment tolerance and facilitates electrical interconnection through the same bonding interface.
3Ease of operation
If conventional electrical TSVs are used on silicon photonic chips, then electrical interconnection through substrate is achieved, but the processing difficulty increases significantly
Solution Approach 1:
The patent extracts the electrical interconnection function from the optical path and implements it through separate electrical contacts on the chip surface. By using surface-mounted electrical contacts rather than through-substrate vias, the processing difficulty is significantly reduced while maintaining electrical interconnection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution simplifies the integration process, improves yield and reduces costs by using mature processes, enhances alignment tolerance, and facilitates high-speed electrical interconnection, making it a versatile platform for multi-layer stacked interconnects and computing chips with optical transceiver I/O ports.
Implementation Method 1
optical signals travel through InP and Si substrates, achieving efficient and high tolerance optical coupling between III-V waveguide layers and SOI or SiN layers
Implementation Method 2
The first interlayer coupling structure in the first layer of optoelectronic chip based on the first substrate converts the light propagating along the optical waveguide in the plane of the first layer of optoelectronic chip into light propagating along the optical through-substrate via in the first substrate through reflection or diffraction mechanism
Implementation Method 3
The first interlayer coupling structure in the first layer of optoelectronic chip based on the first substrate converts the light propagating along the optical waveguide in the plane of the first layer of optoelectronic chip into light propagating along the optical through-substrate via in the first substrate through reflection or diffraction mechanism
Data Source
AI summary
The present invention discloses a heterogeneously integrated optoelectronic chip based on an optical through-substrate via (TSV), comprising multiple stacked optoelectronic chips based on the same or different types of substrates, each layer of optoelectronic chips having several optoelectronic devices, and at least one pair of optoelectronic chip layers are attached back-to-back and have an optical TSV with interlayer coupling structures at both ends, so as to establish optical interconnection between at least one pair of optoelectronic devices in different layers. The interlayer coupling structures include coupling gratings with high alignment tolerance, and a high-reflectivity metal film at a certain distance above the grating to achieve efficient unidirectional coupling. The invention solves the technical difficulties of III-V/silicon heterogeneous integration and 3D multi-chip stacking. It achieves interlayer connections through optical TSVs, enabling front electrodes of optoelectronic chips to be used for interconnection with electronic chips, avoiding the fabrication difficulty of electrical TSVs.