Optical Waveguide Circuit Multi-Layer Wiring Miniaturization
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Solution Overview
Problem
In optical waveguide circuit devices, the miniaturization of the chip size is limited by the size of the wiring line electrode layer formation region, which increases with the number of heaters, leading to decreased manufacturability and insufficient electrical power supply due to reduced width and spacing of these layers.
Innovation Solution
The optical waveguide circuit device features a multi-layer configuration for wiring line electrode layers, where adjacent layers are formed in different wiring layers with a predetermined spacing, allowing for dense arrangement without reducing width or spacing, ensuring adequate electrical power supply and manufacturability while miniaturizing the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of wiring line electrode layers is increased to provide electrical power to more heaters, then the functionality of the optical waveguide circuit device is enhanced, but the chip size increases and manufacturability decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of wiring line electrode layers to a three-dimensional stacked configuration across multiple wiring layers. This vertical stacking allows multiple wiring line electrode layers to be arranged in the thickness direction of the substrate, enabling enhanced functionality with more heaters while maintaining a compact chip size and improving manufacturability by reducing the need for precise lateral spacing.
2Volume of moving object
If the width of wiring line electrode layers is reduced to minimize the wiring line electrode layer formation region, then the chip size is miniaturized, but the allowable current and allowable applied voltage decrease
Solution Approach 1:
The patent resolves this contradiction by arranging wiring line electrode layers in multiple stacked wiring layers rather than reducing their width in a single layer. This vertical arrangement allows each wiring line electrode layer to maintain sufficient width for adequate current and voltage handling while the overall chip size is minimized through the compact multi-layer structure.
3Volume of moving object
If the spacing between adjacent wiring line electrode layers is reduced to minimize the wiring line electrode layer formation region, then the chip size is miniaturized, but the required precision for manufacturing increases
Solution Approach 1:
The patent moves the miniaturization challenge from the lateral dimension to the vertical dimension by stacking wiring line electrode layers in multiple wiring layers. This approach allows larger spacing between adjacent wiring line electrode layers within the same wiring layer, reducing manufacturing precision requirements, while still achieving compact chip size through the multi-layer vertical arrangement.
4Volume of moving object
If the optical waveguide formation region is miniaturized using ZrO2 dopant, then the PLC size is reduced, but the wiring line electrode layer formation region becomes the limiting factor for further miniaturization
Solution Approach 1:
The patent resolves this contradiction by transitioning the wiring line electrode layer arrangement from a two-dimensional planar layout to a three-dimensional stacked configuration across multiple wiring layers. This vertical stacking allows the wiring line electrode layer formation region to be compacted without increasing lateral dimensions, enabling further miniaturization of the PLC beyond what was achievable with optical waveguide formation region reduction alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively miniaturizes the optical waveguide circuit device while maintaining sufficient electrical power delivery and manufacturing precision, achieving a downsized device with improved manufacturability.
Implementation Method 1
a plurality of heaters formed over the cladding layer and over the optical waveguide and configured to heat the optical waveguide
Implementation Method 2
In optical waveguide circuit devices utilizing the Thermo-Optic (TO) effect, heaters and wiring line electrode layers are layered over the PLC cladding layer. The heaters are used to heat the optical waveguides and change their refractive index.
Data Source
AI summary
An optical waveguide circuit device includes: an optical waveguide circuit including a cladding layer formed on a substrate and made from silica-based glass, and an optical waveguide formed within the cladding layer and made from silica-based glass; heaters formed over the cladding layer and the optical waveguide and configured to heat the optical waveguide; wiring line electrode layers formed over the cladding layer, each of the wiring line electrode layers being coupled to a corresponding heater of the heaters and configured to allow electrical power to be supplied to the coupled heater; and an insulating layer covering the cladding layer, the heaters, and the wiring line electrode layers. The wiring line electrode layers adjacent to each other in a plan view are formed in different wiring layers. The wiring line electrode layers adjacent to each other in the same wiring layer are spaced by at least a predetermined distance.