Optically Isolated Via Mask Design for Lithography
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Solution Overview
Problem
As integrated circuit features shrink, the decreasing distance between patterned conductors increases pressure to create smaller vias, leading to conflicts between via patterns and optical proximity correction (OPC) features on photolithographic masks, causing distortion and overlap issues.
Innovation Solution
The via features and associated OPC features are optically isolated on the mask by positioning them such that there is at least one intervening row or column between adjacent via patterns, using a unit cell design that ensures non-overlapping via patterns across the mask, allowing for proper spacing and reduction of distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If OPC features are added to via patterns to reduce distortion, then manufacturing precision is improved, but the area of each via pattern increases causing overlap with adjacent via patterns
Solution Approach 1:
The mask layout is segmented into discrete column positions and row positions, with via patterns placed only at specific intersections. This segmentation allows OPC features to be included within each via pattern while maintaining controlled spacing between patterns through the structured grid system.
Solution Approach 2:
The problem is solved by transitioning from a two-dimensional continuous layout to a discrete grid-based positioning system. By defining specific column and row positions with integer pitch values, the patent creates a structured framework that accommodates both OPC features and spacing requirements through dimensional discretization.
2Productivity
If via sizes are reduced to accommodate smaller pitch, then productivity is improved, but optical isolation between via patterns becomes difficult to maintain
Solution Approach 1:
OPC features are added in advance to via patterns before lithography, pre-compensating for optical distortion effects. This preliminary correction allows smaller via sizes to be used without suffering from the harmful optical interference that would otherwise occur at reduced dimensions.
Solution Approach 2:
The patent changes the positioning parameters by using discrete column and row pitch values to determine via pattern locations. This parameter-based approach ensures adequate optical isolation is maintained even as via sizes are reduced, by systematically controlling the spacing between patterns through the grid structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces distortion and prevents overlap between OPC features, enabling the creation of smaller vias without compromising the integrity of the photolithographic process, thus supporting the shrinking node sizes in integrated circuits.
Implementation Method 1
a lithographic method and mask design wherein the via features and the associated OPC features are optically isolated from each other
Implementation Method 2
optical proximity correction (hereinafter OPC) features are included with the via features in the mask
Data Source
AI summary
A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns.