Co-Packaged Optics Interposer With Misalignment-Tolerant Via Routing
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Solution Overview
Problem
Existing chiplet packaging technologies, such as 2.5D interposer, 2D fan-out, and 2.3D silicon bridge methods, face limitations in area and line input/output density, electrical resistance, and packaging stress management due to thermal expansion mismatches and solder bump pitch.
Innovation Solution
A method involving alignment mark printing, molding, and digital lithography-based interconnect substrate formation, which includes patterning vias and multiple interconnect layers to align and connect chips, eliminating solder interfaces and compensating for misalignments, thereby enhancing interconnect density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If 2.5D interposer method is used, then area density is improved, but line input/output density is limited by solder bump pitch
Solution Approach 1:
The patent replaces the mechanical solder bump interconnection system with a direct wire bond system. Wire bonds can achieve much higher density interconnections compared to solder bumps, thereby increasing line input/output density while maintaining area efficiency. The direct wire bond approach eliminates the solder bump pitch limitation that constrains I/O density in traditional 2.5D interposer methods.
Solution Approach 2:
The patent transitions from planar 2D interconnection to three-dimensional stacking with direct wire bonds extending vertically through the interposer. This dimensional change allows multiple interconnection layers and higher density routing paths, enabling greater line input/output density without increasing the footprint area.
2Adaptability or versatility
If heterogeneous integration is used, then functionality is improved, but alignment issues increase requiring larger interconnect pitch
Solution Approach 1:
The interposer acts as an intermediary component between heterogeneous chips, providing a standardized platform with pre-defined interconnect patterns. This intermediary absorbs and compensates for alignment variations between different chip types, allowing heterogeneous integration without requiring extremely tight alignment precision between mismatched chip interfaces.
Solution Approach 2:
The patent employs parameter changes in the interposer design, including varying interconnect pitch, via dimensions, and routing patterns to optimize alignment tolerance. By adjusting these geometric parameters, the system accommodates manufacturing variations and thermal expansion differences among heterogeneous components while maintaining reliable electrical connections.
3Manufacturing precision
If larger interconnect pitch is used, then alignment tolerance is improved, but interconnect resistivity increases
Solution Approach 1:
The interposer utilizes composite material structures with multiple metal layers and conductive fillers to achieve low resistivity. The composite construction includes copper or aluminum interconnect layers, conductive adhesive materials, and metallic vias, creating a multi-material system that maintains low electrical resistance even with optimized (larger) interconnect pitch for improved alignment tolerance.
4Ease of manufacture
If thermal expansion mismatch is not managed, then manufacturing is simplified, but packaging stress increases causing warpage
Solution Approach 1:
The patent explicitly addresses thermal expansion mismatch by selecting materials with compatible coefficients of thermal expansion (CTE) for the interposer and attached chips. The interposer material is chosen to intermediate between chips with different CTE values, reducing thermal stress during temperature cycling. This material selection strategy prevents warpage and reliability failures while maintaining manufacturability.
Data Source
AI summary
A method of forming a packaged multichip module includes molding a set of chips in a medium, mapping a position and orientation of the chips, forming an interconnect substrate. The forming of the interconnect structure including patterning a first interconnect layer to form a first plurality of patterned vias that each have an opening that is configured to connect with an interconnect formed on the chips based at least in part on the position and orientation information, and bonding the interconnect substrate to the multichip module. The bonding includes positioning and aligning the interconnect substrate to the chips such that the interconnects are aligned with the first plurality of patterned vias and attaching a stacked chip to the multichip module via the interconnect substrate, wherein interconnects of the stacked chip are electrically coupled to conductive layers formed in the first plurality of patterned vias of the first interconnect layer.