Optimization Apparatus Weight Coefficient Segmentation

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Solution Overview

Problem

Conventional optimization apparatuses face challenges in handling large-scale multivariable optimization problems due to the increasing number of weight coefficients, which exceeds the storage capacity of one-chip semiconductor integrated circuits, leading to slowed calculation speeds and memory access issues.

Innovation Solution

The optimization system employs multiple optimization apparatuses, each storing a subset of weight coefficients and using bit value calculation circuits to determine energy changes and accept updates based on thermal excitation energy and temperature parameters, with a second selection circuit coordinating the updates across the apparatuses to reduce memory access and communication overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of bits increases to handle larger problem scales, then the optimization capability improves, but the number of weight coefficients increases causing storage capacity to be exceeded and calculation speed to slow down

Engineering Contradiction:
Improveoptimization capabilityVSAvoidcalculation speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent divides the weight coefficients into multiple groups and stores them in different storage units within the optimization apparatus. Each storage unit holds a subset of weight coefficients, allowing the system to handle larger problem scales without requiring a single large storage unit that would slow down access. This segmentation enables parallel access to different weight coefficient groups, maintaining calculation speed while increasing optimization capability.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If weight coefficients are stored in external memory to overcome storage limitations, then storage capacity increases, but memory access time increases slowing down calculation

Engineering Contradiction:
Improvestorage capacityVSAvoidmemory access time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent implements a hierarchical storage structure where weight coefficients are organized in nested storage units. The system includes multiple levels of storage with different access speeds, and frequently accessed weight coefficients are kept in faster storage units while less frequently accessed coefficients are stored in slower units. This nesting approach provides large effective storage capacity while maintaining fast access times for critical operations.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Productivity

If multiple optimization apparatuses are used to handle large-scale problems, then processing capability improves, but communication overhead between apparatuses increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidcommunication overhead
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines multiple optimization apparatuses into a unified system where the selection circuits coordinate updates across all apparatuses. The bit value calculation circuits in each apparatus work in parallel, and the selection circuits merge their results to determine the next state update. This merging approach enables the system to handle large-scale problems with high processing capability while minimizing communication overhead by reducing the frequency and volume of inter-apparatus communications.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11468287B2Information processing system, information processing apparatus, and information processing method
Publication Date: 2022.10.11 FUJITSU LTD
  • US11468287B2 patent drawing
  • US11468287B2 patent drawing
  • US11468287B2 patent drawing

AI summary

Storage devices each hold corresponding one of n weight coefficient groups obtained by dividing weight coefficients such that each group includes weight coefficients about at least two bits. Bit value calculation circuits each output a result (flag information) by determining whether to accept updating about each of the bits based on the weight coefficient group, a value of an updated bit, identification information, and thermal excitation energy and an updated value of an accepted bit whose uprate has been accepted. First selection circuits each select an accepted bit based on the flag information and output a state signal including the flag information, the updated value, and identification information associated with the accepted bit. A second selection circuit determines the updated bit based on the flag information in the state signal and supplies the value of the updated bit and the identification information to each of optimization apparatuses.