Optoelectronic Component Alignment via Cadmium-Selective Etching

Solution Overview

Problem

Existing methods for manufacturing optoelectronic components, such as matrix detectors, face challenges in aligning optical elements with diode-type structures due to the lack of correlation between marking zones and the actual positioning of these structures, leading to potential misalignment and dysfunction.

Innovation Solution

A method for creating a first support with alignment marks on the second face that are directly correlated with the diode-type structures, involving a substrate with a cadmium-based support layer and semiconductor layer, where arsenic is implanted to form doped zones and an alignment mark with a higher cadmium atomic proportion, allowing precise alignment during assembly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If marking zones are provided on the first support to facilitate alignment of the second support, then the alignment ease is improved, but the marking zones are not correlated with the actual positioning of the diode type structures leading to misalignment

Engineering Contradiction:
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The invention merges the alignment mark formation with the diode structure formation process. Both the diode type structures and the alignment marks are created simultaneously through the same epitaxial growth process on the substrate, ensuring that the alignment marks are inherently correlated with the actual positioning of the diode structures. This eliminates the discrepancy between marking zones and actual structure positions while maintaining ease of alignment.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The alignment marks are formed in advance during the epitaxial growth process before the substrate is removed. By creating the alignment marks preliminarily along with the diode structures during the same growth phase, the marks are guaranteed to be in the correct positions relative to the structures, enabling precise alignment when the supports are assembled.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If the substrate is removed to form the first support, then the first support is obtained for assembly, but the alignment marks must remain correlated with the structures after substrate removal

Engineering Contradiction:
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The alignment marks and diode structures are merged in their formation process through simultaneous epitaxial growth. This ensures that both features are created from the same reference frame (the substrate position), so when the substrate is removed, the marks remain correlated with the structures without requiring additional positioning steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The substrate serves as an intermediary during the formation process. By forming both the diode structures and alignment marks on the substrate during epitaxial growth, the substrate acts as a common reference frame that ensures positional correlation. After the marks and structures are formed, the substrate can be removed while the marks and structures maintain their relative positioning.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Ensures proper alignment between optical elements and diode-type structures, enhancing the manufacturing process and reducing the risk of component dysfunction by using etching techniques sensitive to cadmium proportion to create a visible height difference for alignment.

Implementation Method 1

implanting in a localised manner arsenic of the semiconductor layer through the first surface on a plurality of first locations of the semiconductor layer and at a second location located in the aperture

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Implementation Method 2

allowing cadmium diffusion from the support layer to the second location, said diffusion being promoted by the arsenic implanted in said second location

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 3

heat treating able to activate the implanted arsenic on the plurality of first locations to form doped zones of a second conductivity type... the heat treatment being also adapted to allow cadmium diffusion from the support layer to the second location

Methodology Applied
Scientific EffectThermal Diffusion: Diffusion

Implementation Method 4

heat treating able to activate the implanted arsenic

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 5

removing the support layer and a part of the thickness of the semiconductor layer by means of an etching sensitive to the cadmium atomic proportion such that the second surface of the semiconductor layer has a height difference between the alignment mark and the rest of the second surface

Methodology Applied
Scientific EffectSelective Etching:

Data Source

PatentUS10923524B2Support for forming an optoelectronic component, optoelectronic component and method for manufacturing such a support and such a component
Publication Date: 2021.02.16
  • US10923524B2 patent drawing
  • US10923524B2 patent drawing
  • US10923524B2 patent drawing

AI summary

The invention relates to a method for manufacturing a first support (100) for forming, in particular with a functionalised second support (200), an optoelectronic component (1), the first support (100) comprising a semiconductor layer (110) and an alignment mark (140) provided on said semiconductor layer (110). The manufacturing method includes in particular a step of forming an aperture (141) in a semiconductor layer (110) comprising cadmium, a step of diffusing cadmium in a second location (142) of the aperture (141) and a cadmium sensitive etching step for promoting etching of one from the second location (142) which is rich in cadmium and the rest of a surface (110B) of the semiconductor layer (110). The invention also relates to a first support (100).