Optoelectronic Carrier With Structured Conductive Layer
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Solution Overview
Problem
Existing optoelectronic semiconductor chips face challenges in achieving both electrical and mechanical stability, particularly when handling high currents and maintaining structural integrity after substrate removal, while also avoiding issues like electric field spikes and diffusion processes.
Innovation Solution
A carrier for optoelectronic structures is designed with an electrically insulating main body, structured conductive layers, and a carrier-side connecting means layer, which provides mechanical support, electrical connections, and current distribution, using insulation and passivation materials to manage potential differences and prevent diffusion, while allowing for efficient connection and redistribution of currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a substrate is removed to create thin optoelectronic structures, then device miniaturization and integration are improved, but mechanical stability and structural integrity deteriorate
Solution Approach 1:
The patent introduces a carrier as an intermediary component that provides mechanical support to the thin optoelectronic structure. The carrier has a first side for receiving the optoelectronic structure and a second side for mounting, acting as a mediator between the fragile thin structure and the mounting substrate. This allows the structure to be thin and integrated while maintaining mechanical stability through the carrier's support.
2Power
If high currents are handled to improve power output, then device performance is improved, but electrical breakdown and diffusion processes worsen
Solution Approach 1:
The patent implements an electrically conductive layer that extends from the first side to the second side of the carrier, creating equipotential regions that distribute electrical potential evenly. This conductive layer includes connection regions for current input and output, allowing high currents to be handled while preventing electrical breakdown through uniform potential distribution and controlled current paths.
3Ease of operation
If connection locations are provided for current input and output, then electrical functionality is improved, but risk of electric field spikes and diffusion increases
Solution Approach 1:
The patent applies different material properties to different regions of the carrier. The first side has properties optimized for receiving and protecting the optoelectronic structure, while the second side has properties optimized for mounting and electrical connection. The conductive layer has specific regions for current input and output with localized properties that manage electric field distribution, preventing spikes and diffusion at connection points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the creation of a stable optoelectronic semiconductor chip with improved electrical and mechanical stability, preventing electric breakdowns and diffusion processes, and allowing for efficient current distribution and connection, even in thin structures.
Implementation Method 1
The electrically insulating main body is formed with an electrically insulating material or with electrically insulating materials
Implementation Method 2
Via the structured electrically conductive layer, the current impressed through the connection locations is distributed along the top side of the carrier or conducted to the desired locations
Implementation Method 3
The connecting means layer is for example a solder layer or a layer composed of conductive adhesive
Data Source
AI summary
A carrier (1) for an optoelectronic structure (2) is specified, wherein in places an electrically insulating passivation material (16) is arranged between an electrically conductive layer (14) of the carrier (1) and a carrier-side connecting means layer (15). Furthermore, an optoelectronic semiconductor chip comprising such a carrier and an optoelectronic structure (2) is specified, said structure being electrically conductively and mechanically connected to the carrier (1) by means of the carrier-side connecting means layer (15).