Optoelectronic Semiconductor Chip Carrier with Multi-Layer Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Optoelectronic semiconductor chips, such as light-emitting diodes, face challenges due to high series resistances in carriers, which hinder efficient operation.
Innovation Solution
A carrier design with a carrier body featuring electrical vias and insulation layers that allow for partial coverage of the through-connections, enabling adjustable via sizes and reduced series resistance, while incorporating a diode structure for electrostatic discharge protection and using silicon for cost-effectiveness and microstructurability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a carrier with electrical vias is used to contact semiconductor bodies from the rear side, then electrical contact is achieved, but the series resistance is comparatively high which hinders efficient operation
Solution Approach 1:
The patent transitions from a single-layer via structure to a multi-layer via structure with at least two insulation layers and multiple connection surfaces at different depths. This dimensional expansion allows the via to maintain electrical connectivity while reducing series resistance through increased conductive path area, directly resolving the contradiction between reliable contact and energy loss.
Solution Approach 2:
The via structure employs composite material design with multiple insulation layers (different materials or configurations) and conductive materials arranged in specific patterns. This composite approach optimizes both electrical conductivity (reducing series resistance) and insulation performance (maintaining contact reliability) simultaneously.
2Loss of energy
If the cross section of the via is increased to reduce series resistance, then series resistance decreases, but the opening area must also be increased which may affect other design parameters
Solution Approach 1:
The patent resolves this area constraint by expanding the via structure into the third dimension with multiple insulation layers and connection surfaces at different depths. This allows the effective conductive cross-section to be increased without proportionally increasing the top opening area, as the additional conductive area is achieved through vertical layering rather than horizontal expansion.
Solution Approach 2:
The multi-layer via structure implements a nested configuration where connection surfaces and insulation layers are arranged concentrically or in nested patterns. This nesting allows maximum conductive material utilization within the constrained opening area, increasing effective cross-section without excessive opening size increase.
3Reliability
If insulation layers are added to electrically insulate the via from the carrier body, then electrical insulation is achieved, but the device complexity increases
Solution Approach 1:
The multi-layer via structure serves multiple functions simultaneously: the first and second insulation layers provide electrical insulation, the multiple connection surfaces provide electrical connectivity, and the overall structure reduces series resistance. This multi-functionality means that while the structure appears more complex, each additional layer contributes multiple benefits, effectively managing the complexity-performance trade-off.
Solution Approach 2:
The patent merges insulation and conduction functions within a unified via structure rather than treating them as separate components. The insulation layers and connection surfaces are integrated in a single via formation process, combining what could be separate operations into one structured unit, thereby managing overall device complexity.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A support for an optoelectronic semiconductor chip is specified, wherein the support (1) has a support body (2) with a first main face (21) and a second main face (22), which is opposite the first main face (21). The support body (2) has at least one electrical plated-through hole (31) made in it which extends from the first main face (21) to the second main face (22). The first main face (21) has an insulating layer (4) arranged on it which covers only regions of the electrical plated-through hole (31). In addition, an optoelectronic semiconductor chip (10) having such a support (1) is specified.