Optoelectronic Chip Barrier for Bonding Material Control
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Solution Overview
Problem
Optoelectronic semiconductor chips face issues during soldering or adhesive bonding, where the bonding material can flow or creep onto the chip's side face, potentially short-circuiting the p-n junction, leading to inefficiencies and risks of shunts and aging problems.
Innovation Solution
A barrier is formed on the optoelectronic semiconductor chip or carrier to prevent bonding material from flowing, using a semiconductor layer sequence with elevations or troughs that act as a dam, ensuring cohesive bonding and maintaining a defined distance between the chip and the carrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If cohesive bonding is performed to bond the semiconductor chip to the carrier, then bonding strength is improved, but bonding material may flow onto the chip side face causing short circuits
Solution Approach 1:
A barrier structure is introduced as an intermediary element between the bonding material and the semiconductor chip side face. This barrier prevents direct contact between the flowing bonding material and the chip, eliminating the short circuit risk while allowing cohesive bonding to proceed with adequate strength.
Solution Approach 2:
The bonding area is segmented into distinct zones: a bonding area where bonding material is applied, and a barrier area that prevents material flow onto the chip side face. This segmentation is achieved through structured barriers or elevated regions that create spatial separation between functional areas.
2Reliability
If bonding material is applied generously to ensure cohesive bonding, then bonding reliability is improved, but excess material flows beyond chip edges
Solution Approach 1:
Different regions of the bonding interface are given different properties: the bonding area has high material affinity and accessibility, while the barrier areas have material-repelling characteristics or geometric constraints that prevent overflow. This local differentiation allows generous material application without loss of containment.
3Manufacturing precision
If pressure is increased during bonding to improve contact, then bonding quality is improved, but bonding material is pushed beyond chip edges
Solution Approach 1:
Barrier structures are prepared in advance on the chip or carrier surface to counteract the harmful effect of pressure-induced material extrusion. These pre-formed barriers create geometric or surface property constraints that prevent material flow in critical directions even when bonding pressure is applied.
4Device complexity
If no barrier is used to simplify the structure, then device complexity is reduced, but bonding material short-circuits the p-n junction
Solution Approach 1:
The barrier function is merged with existing chip or carrier structures rather than being implemented as a separate component. For example, elevated regions of the substrate or patterned barrier layers are integrated into the bonding interface design, providing protection without adding discrete parts.
Data Source
AI summary
An optoelectronic lighting device includes an optoelectronic semiconductor chip including a top side and an underside opposite the top side, wherein a semiconductor layer sequence is formed between the top side and the underside, the semiconductor layer sequence includes an active zone that generates electromagnetic radiation, and a barrier for a bonding material flowing on account of cohesive bonding of the semiconductor chip to a carrier is formed at one of the top side and the underside.