Optoelectronic Semiconductor Chip Deep Etching via Composite Protective Layer
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Solution Overview
Problem
Existing optoelectronic semiconductor chips face limitations in etching depth and mirror layer quality due to the limited selectivity of SiO2 etching masks and the need for an opening step for electrical contacting, which impairs adhesion and reduces the quality of the mirror layer.
Innovation Solution
The method involves structuring an optoelectronic semiconductor chip with a semiconductor body having a first and second semiconductor region, an active zone, an electrically conductive contact layer, and a mirror layer, where the contact layer is laterally extended to create an interspace for a protective layer, allowing for deeper etching and direct electrical contacting without an opening step, using Ni for the contact layer and Ag or Ag-based materials for the mirror layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick protective layer of SiO2 is used as an etching mask, then the semiconductor body can be protected during etching, but the selectivity of the etching mask is limited so that the semiconductor body cannot be etched to any depth
Solution Approach 1:
The patent segments the protective layer into two distinct materials: SiO2 for the lower portion (first protective layer) and SiN for the upper portion (second protective layer). This segmentation allows each material to perform its function optimally - SiO2 provides good etching selectivity for deep etching, while SiN provides superior adhesion and protection during subsequent processing steps.
Solution Approach 2:
The patent employs a composite protective layer structure combining SiO2 and SiN materials. This composite approach leverages the complementary properties of both materials: SiO2's high etching selectivity enables deep etching depths exceeding 2 μm, while SiN's excellent adhesion properties prevent delamination during the deep etching process and subsequent metallization steps.
2Reliability
If the mirror layer is covered with an electrically insulating protective layer, then the mirror layer is protected, but an opening step is necessary for contacting which either impairs adhesion of the protective layer around the opening and/or reduces the quality of the mirror layer
Solution Approach 1:
The patent applies the protective layer (both SiO2 and SiN layers) before forming the contact openings. This preliminary application ensures that the protective layer is already in place to protect the mirror layer during subsequent processing, and the contact openings are formed through controlled etching that maintains the integrity and quality of both the mirror layer and protective layer edges.
3Ease of manufacture
If the protective layer is used as an etching mask, then the semiconductor body can be structured, but the selectivity is limited reducing productivity for deep etching applications
Solution Approach 1:
The patent changes the material parameter of the protective layer from a single material (SiO2) to a composite structure (SiO2 + SiN). This parameter change fundamentally alters the etching characteristics, enabling selective etching of the semiconductor body to depths exceeding 2 μm while maintaining protective layer integrity and preventing adhesion issues during deep etching processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of the mirror layer, allows for deeper etching, and eliminates the need for an opening step, resulting in improved adhesion and reduced quality issues, achieving etching depths greater than 2 μm with high selectivity and maintaining the integrity of the mirror layer.
Implementation Method 1
Known optoelectronic semiconductor chips comprise a mirror layer on the semiconductor body to reflect the electromagnetic radiation emitted by the active zone
Implementation Method 2
the electrically conductive contact layer consists of Ni
Data Source
AI summary
An optoelectronic semiconductor chip includes a semiconductor body including a first semiconductor region, a second semiconductor region and an active zone disposed between the first and second semiconductor regions, an electrically conductive contact layer arranged on a side of the first semiconductor region facing away from the second semiconductor region, and an electrically conductive mirror layer arranged between the first semiconductor region and the electrically conductive contact layer, and laterally protruding at the edge by the first semiconductor region and the electrically conductive contact layer so that between the first semiconductor region and the electrically conductive contact layer there is an interspace in which a protective layer is arranged for protecting the mirror layer, wherein the electrically conductive contact layer extends laterally to an edge of the first semiconductor region, and the electrically conductive contact layer consists of Ni.