Optoelectronic Semiconductor Chip Depression Solder Filling
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Solution Overview
Problem
Optoelectronic semiconductor chips face efficiency and usability issues due to the risk of incomplete solder filling in blind holes, leading to cavities between the semiconductor body and the carrier plate, which can result in reduced performance or render the chip unusable.
Innovation Solution
The semiconductor chip design features a depression with a metal layer that extends from the rear side into the semiconductor layer sequence, ensuring the solder fills the depression, and an electrically insulating layer is used to cover the active layer, reducing the risk of short circuits and cavity formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If blind holes are used for soldering connection, then electrical connection is achieved, but cavities may remain between the semiconductor body and carrier plate
Solution Approach 1:
The blind hole is divided into two functional sections: a first section for electrical connection and a second section for solder filling. This segmentation allows each section to serve its specific purpose effectively, ensuring complete solder filling while maintaining electrical connectivity.
Solution Approach 2:
Different regions of the depression are assigned different properties: the first section provides electrical connection functionality while the second section is optimized for solder filling. This local differentiation ensures that each area performs its intended function optimally without compromising the other.
2Manufacturing precision
If metal layer is added to fill depression, then solder filling is improved, but manufacturing complexity increases
Solution Approach 1:
The metal layer is deposited in advance during the manufacturing process, before soldering occurs. This preliminary action prepares the depression structure to guide solder filling effectively, ensuring complete filling while integrating the metal layer deposition into the existing manufacturing workflow.
3Reliability
If electrically insulating layer is applied, then short circuit risk is reduced, but manufacturing steps increase
Solution Approach 1:
An electrically insulating layer is introduced as an intermediary between the metal layer and the active semiconductor layer. This intermediary prevents direct electrical contact that could cause short circuits, while the layer is positioned and configured to minimize its impact on the overall device structure.
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present application relates to an optoelectronic semiconductor body (1), comprising a front face (120), which is provided to emit and/or receive electromagnetic radiation, a rear face (110), which is located opposite of the front face (120) and which is provided for application on a support plate (7), and an active semiconductor layer sequence (2), which, in the direction from the rear face (110) to the front face (120), comprises a layer of a first conductivity type (21), an active layer (22), and a layer of a second conductivity type (23) in this order. The present application further relates to a semiconductor chip comprising such a semiconductor body (1).