Optoelectronic Semiconductor Chip Mirror Potential Design
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Solution Overview
Problem
Optoelectronic semiconductor chips face issues with aging behavior and efficiency due to moisture-induced ion migration, leading to electrical shunts and reduced reliability.
Innovation Solution
The design incorporates a first mirror with a metallic layer at a potential different from the p-conducting region, reducing ion migration and using a p-metallization at the same potential as the p-conducting region, with openings for electrical connection, and dielectric layers for insulation and moisture protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metallic layer is used for electrical connection, then electrical conductivity is improved, but ion migration and cation formation occur leading to reduced reliability
Solution Approach 1:
The patent applies equipotentiality by connecting the metallic layer to the n-conducting region instead of the p-conducting region. During operation, the n-conducting region maintains a constant negative potential, while the p-conducting region has a positive potential. By establishing the metallic layer at the same electrical potential as the n-conducting region through electrical conductive connection, ion migration is suppressed because there is no potential difference driving ions toward the metallic layer.
2Ease of manufacture
If the metallic layer is electrically connected to the p-conducting region, then electrical connection is simplified, but cation formation increases reducing efficiency
Solution Approach 1:
The patent connects the metallic layer to the n-conducting region to establish equipotential conditions. During operation, the n-conducting region is at a constant negative potential, preventing cation formation at the metallic layer interface. This connection requires passing through the p-conducting region and active region, but this path ensures the metallic layer remains at negative potential, suppressing ion migration and cation formation.
3Reliability
If the metallic layer is at the same potential as the p-conducting region, then electrical connection is direct, but moisture-induced ion migration occurs
Solution Approach 1:
The patent establishes the metallic layer at the same electrical potential as the n-conducting region through electrical conductive connection. During operation, the n-conducting region maintains a constant negative potential, creating equipotential conditions between the metallic layer and the semiconductor body. This eliminates the potential difference that would otherwise drive moisture-induced ion migration, thereby improving reliability and efficiency.
4Reliability
If openings are made in the first mirror for electrical connection, then electrical conductivity is enabled, but reflection efficiency is reduced
Solution Approach 1:
The patent applies local quality by creating localized openings in the first mirror only where electrical connection is required. The mirror structure is maintained with high reflectivity in all other areas. The openings are positioned specifically to allow electrical conductive connection between the p-metallization and the p-conducting region, while the surrounding mirror areas continue to provide efficient electromagnetic radiation reflection and decoupling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement enhances the reliability and efficiency of the semiconductor chip by reducing cation formation, improving moisture resistance, and allowing for efficient reflection and decoupling of electromagnetic radiation.
Implementation Method 1
a first mirror containing a first metallic layer... allowing for efficient reflection and decoupling of electromagnetic radiation
Data Source
AI summary
An optoelectronic semiconductor chip includes a semiconductor body including an n-conducting region, a p-conducting region and an active region between the n-conducting region and the p-conducting region; a first mirror containing a first metallic layer, and a p-metallization containing a second metallic layer, wherein during operation of the semiconductor chip, the first mirror is not at the same electrical potential as the p-conducting region, during operation of the semiconductor chip, the p-metallization is at the same electrical potential as the p-conducting region, and the first mirror has at least one opening through which the p-metallization is electrically conductively connected to the p-conducting region.