Optoelectronic Semiconductor Chip Narrow Trench Singulation
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Solution Overview
Problem
Conventional methods for manufacturing optoelectronic semiconductor chips result in high epitaxial material waste and inaccuracies due to wide separation trenches, which can damage the active layers and reduce luminous efficiency.
Innovation Solution
A method using directional dry etching to form narrow separation trenches, allowing for the efficient singulation of optoelectronic semiconductor chips with minimal epitaxial material loss, and the application of an ALD layer for encapsulation and protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional separation methods are used, then manufacturing process is simple, but separation trench width is large causing material waste and potential damage to active layers
Solution Approach 1:
The separation process is divided into multiple sequential steps: forming mask pattern, directional dry etching to create separation trenches, and selective removal of sacrificial layers. This segmentation allows precise control of trench width while managing process complexity through systematic breakdown of operations
Solution Approach 2:
A mask pattern is formed in advance on the semiconductor layer before etching. This preliminary action defines the precise location and width of separation trenches, enabling accurate material removal while protecting active layers from damage
2Productivity
If wide separation trenches are formed, then manufacturing is easier, but epitaxial material waste increases and luminous efficiency decreases
Solution Approach 1:
The etching parameters are optimized to achieve highly anisotropic etching with vertical profile. By controlling etch rate, plasma chemistry, and process conditions, the separation trench width is precisely controlled to minimize material waste while maintaining ease of manufacture through standardized process parameters
Solution Approach 2:
A sacrificial layer is introduced as an intermediary element between the semiconductor layers. This layer facilitates clean separation and can be selectively removed after trench formation, enabling precise control of separation geometry while simplifying the overall manufacturing process
3Manufacturing precision
If directional dry etching is used, then separation trench precision is improved, but manufacturing process complexity increases
Solution Approach 1:
Conventional mechanical sawing or laser separation is replaced with directional dry etching. This substitution achieves superior precision by using plasma chemistry and physical sputtering mechanisms rather than mechanical cutting, while the process complexity is managed through automated semiconductor manufacturing equipment
4Reliability
If separation trenches are formed too deeply, then complete separation is achieved, but risk of damaging active layers increases
Solution Approach 1:
The etching process exhibits spatially selective removal of material. The separation trenches are etched to a controlled depth that provides complete separation at the carrier interface while stopping before reaching the active layers. This local quality control ensures reliability of separation without harmful effects on functional regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces material waste, enhances luminous efficiency by minimizing trench width, and improves the manufacturing process flow with precise trench formation and encapsulation for better chip performance.
Implementation Method 1
forming a plurality of separation trenches in the laminar structure along a singulation pattern using at least one directional dry etching method
Implementation Method 2
The dry etching method used is at least partially a strongly anisotropic dry etching method. For example, the dry etching method takes place using a chlorine plasma and/or a fluorine plasma
Implementation Method 3
the application of an ALD layer for encapsulation and protection
Data Source
AI summary
Disclosed is an optoelectronic semiconductor chip (10) comprising: —a succession of semiconductor layers (1) that has a main plane of extension, an active layer (12) and a bottom surface (1c); —a substrate (41) that is arranged on the bottom surface (1c) of the succession of semiconductor layers (1) and has a base surface (41c) facing away from the bottom surface (1c); and —a succession of joining layers (3) which is arranged in at least some locations between the succession of semiconductor layers (1) and the substrate (41) in a vertical direction; wherein —the substrate (41) laterally protrudes from the succession of semiconductor layers (1) by a maximum of 10 μm.