3D Optoelectronic Package Layout for Shorter Signal Paths
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Solution Overview
Problem
Current optoelectronic components in mobile and wearable devices face challenges in integration with other electronic components, hindering the reduction in device size and affecting electrical signal transmission quality.
Innovation Solution
An optoelectronic package design featuring a first redistribution layer, metal pillars, optoelectronic chips, insulation layers, and processing components, with electrical connections through metal pillars and redistribution layers to shorten the distance between chips and processing components, facilitating size reduction and improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If optoelectronic components are integrated with other electronic components, then device size can be reduced, but the integration complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical stacking, where the optoelectronic chip is mounted on the substrate and the processing component is positioned above it, connected through vertical conductive vias. This dimensional change enables compact integration while maintaining functional separation and reducing signal transmission distance.
Solution Approach 2:
The patent implements a nested structure where the processing component is positioned above the substrate and optoelectronic chip, with conductive vias penetrating through multiple layers to establish electrical connections. This nested arrangement allows multiple functional components to occupy different vertical levels within a compact footprint, effectively integrating multiple components without increasing planar area.
2Reliability
If the distance between optoelectronic chips and processing components is reduced, then signal transmission quality improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a substrate with conductive vias as an intermediary structure that pre-establishes electrical connection paths before component mounting. The vias are formed with precise positioning on the substrate, serving as alignment references for mounting the optoelectronic chip and processing component, thereby reducing the cumulative alignment error that would otherwise accumulate through multiple separate bonding steps.
3Ease of manufacture
If conventional integration methods are used, then manufacturing processes are simpler, but device size reduction is hindered
Solution Approach 1:
The patent performs preliminary actions by pre-forming conductive vias with electrical connection structures on the substrate before mounting the optoelectronic chip and processing component. This preliminary preparation of connection paths simplifies the subsequent assembly process, as components can be directly mounted and connected without requiring complex post-assembly routing or wiring operations.
Data Source
AI summary
An optoelectronic package includes a first and a second redistribution layers, a plurality of first and second metal pillars, an optoelectronic chip, a first and a second insulation layers and a processing component. The first metal pillars are disposed on the first redistribution layer. The optoelectronic chip includes a wiring layer, an active structure and a main layer. The wiring layer is electrically connected to the first metal pillars. The main layer is disposed between the wiring layer and the active structure. The first insulation layer disposed on the first redistribution layer covers the optoelectronic chip and the first metal pillars. The processing component is electrically connected to the first redistribution layer which is located between the processing component and the optoelectronic chip. The second metal pillars and the second insulation layer are disposed between the first redistribution layer and the second redistribution layer.