Optoelectronic Packaging via 3D Stacked Carrier Substrates
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Solution Overview
Problem
Existing optoelectronic integrated semiconductor packaging structures face challenges in achieving high-density integration due to the mismatch between silicon optical process nodes and electrical chip process nodes, leading to difficulties in meeting the requirements of high-density packaging, signal attenuation, and energy consumption.
Innovation Solution
The method involves using a TSV substrate with metal pillars, redistribution layers, optical waveguide wiring, micro-mirrors, and supporting substrates to stack and interconnect electrical and optical signal wirings, reducing packaging area and signal transmission paths, and incorporating a heat dissipation member for efficient energy management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If direct bonding of optical chip and electrical chip to base substrate is used, then packaging structure is simple, but high-density integration requirement cannot be met
Solution Approach 1:
The patent introduces intermediate carrier substrates (first and second carrier substrates) that enable three-dimensional stacking of optical and electrical chips. This vertical dimensionality change allows high-density integration by stacking components in multiple layers rather than arranging them in a single plane, thereby achieving compact packaging while meeting high-density requirements.
Solution Approach 2:
The packaging structure is segmented into multiple functional modules: optical chip, electrical chip, first carrier substrate, second carrier substrate, and base substrate. Each segment performs a specific function and can be independently optimized. This segmentation allows for precise positioning and high-density integration while maintaining structural simplicity through modular assembly.
2Length of moving object
If signal transmission paths are long, then chip size is large, but signal attenuation increases
Solution Approach 1:
The patent uses vertical stacking via carrier substrates to shorten horizontal signal transmission paths. By transitioning from planar arrangement to three-dimensional stacking, the signal transmission distance is significantly reduced, thereby lowering signal attenuation while maintaining compact chip size.
3Ease of manufacture
If optical chip and electrical chip are packaged separately, then manufacturing is simple, but I/O bandwidth is limited
Solution Approach 1:
The patent merges optical chip and electrical chip packaging into a single integrated structure using carrier substrates. The optical chip is mounted on the first carrier substrate, which is then integrated with the second carrier substrate carrying the electrical chip. This merged structure enables high-speed optical-electrical interconnection, significantly increasing I/O bandwidth while maintaining manufacturing feasibility through standardized mounting processes.
4Power
If energy consumption is high, then system performance is good, but power consumption increases
Solution Approach 1:
The patent replaces traditional electrical signal transmission with optical signal transmission for high-bandwidth data communication. By using optical interconnection between chips, the system achieves high performance with lower energy consumption, as optical transmission is more energy-efficient for high-speed data transfer compared to electrical transmission over long distances.
Data Source
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AI summary
The present invention provides a photoelectric integrated semiconductor packaging structure and a manufacturing method therefor. By means of a TSV base, a substrate, a rewiring layer, an optical waveguide wiring layer, and a micro-mirror, an optical chip and an electrical chip are packaged. In this way, the stacked interconnection and interlaced routing of electrical signal wiring and optical signal wiring can be achieved, thereby reducing the packaging area, increasing the wiring density, effectively shortening transmission paths of optical signals and electrical signals, reducing signal attenuation, and meeting the requirements of high-density integrated packaging.