Order Offset Correction Circuit for Display Driving Irregularities

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Solution Overview

Problem

High-definition imaging technologies face display irregularities due to small grayscale voltage errors, leading to issues like streaks in liquid crystal projectors, as existing multiplex driving methods fail to effectively correct order and position offsets in data signals.

Innovation Solution

An integrated circuit device with a data line driving circuit, order offset register, and order setting circuit that corrects order offsets by adding offset correction values to image data based on stored setting values, preventing display irregularities by adjusting the driving order of pixels and using demultiplexing switch elements to control data signal distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiplex driving is used to drive multiple data lines, then productivity is improved, but order offsets are generated causing display irregularity

Engineering Contradiction:
Improvedata writing speedVSAvoiddisplay quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing order offset correction values in an offset register before the actual data writing process. The correction values are prepared in advance based on the driving order, and the gamma correction circuit applies these corrections proactively to each data signal before it reaches the liquid crystal panel, thereby preventing display irregularity from occurring in the first place

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by establishing a correction mechanism where the system actively monitors and compensates for order offsets. The gamma correction circuit uses pre-stored correction values to adjust each data signal based on its position in the multiplex driving sequence, creating a closed-loop correction system that ensures consistent display quality across all data lines despite the multiplexing process

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If grayscale voltage is reduced for higher definition, then manufacturing precision is improved, but display irregularity increases due to small voltage errors

Engineering Contradiction:
Improvegrayscale precisionVSAvoiddisplay uniformity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting the voltage parameters of data signals through gamma correction. The correction circuit modifies voltage levels based on pre-stored correction values that compensate for order offsets, ensuring that even with reduced grayscale voltage steps for high definition, the display maintains uniformity and avoids irregularity caused by small voltage errors

Inventive Principle:
Principle #35Parameter changes

3Productivity

If data voltages are multiplex driven, then productivity is improved, but position offsets caused by leak currents and parasitic capacitances occur

Engineering Contradiction:
Improvewriting efficiencyVSAvoidvoltage accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by pre-calculating position offset correction values for each data line and storing them in the offset register before multiplex driving begins. These corrections are prepared in advance to compensate for expected leak currents and parasitic capacitance effects, allowing the system to maintain voltage accuracy throughout the high-speed multiplex writing process

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8400439B2Integrated circuit device, electro optical device and electronic apparatus
Publication Date: 2013.03.19 SEIKO EPSON CORP
  • US8400439B2 patent drawing
  • US8400439B2 patent drawing
  • US8400439B2 patent drawing

AI summary

An integrated circuit device includes: a data line driving circuit provided for each of a plurality of data signal supply lines that supplies a multiplexed data signal to a corresponding data signal supply line; an order offset register that stores a first order offset setting value; an order setting circuit that sets the order of driving the first pixel; and an order offset addition circuit corresponding to the data line driving circuit. When the data line driving circuit drives the q-th (q is a natural number less than p) pixel in the r-th (r is a natural number less than p) place in the order, the order offset addition circuit processes addition of an order offset correction value based on the r-th order offset setting value among the first order offset setting value.