Ordered Set Error Protection for High-Speed Interconnects
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Solution Overview
Problem
Existing error protection mechanisms for ordered sets in high-speed interconnects, such as PCIe Gen 6, are inadequate due to the unscrambled nature of ordered sets like EIEOS and variable length of SKP OS, making them vulnerable to high bit error rates, which can lead to link failures and inefficiencies.
Innovation Solution
The solution involves partitioning each 128-bit ordered set into two 64-bit chunks, applying CRC/parity protection to each chunk, and ensuring both chunks are correct for critical ordered sets like SKP OS and EIEOS, while using control payload flits for non-scrambled sets like EIOS, thereby maintaining reliability and availability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing error protection mechanisms are used for ordered sets, then the interconnect can operate at high speeds, but the bit error rate becomes unacceptably high leading to link failures
Solution Approach 1:
The patent segments the 128-bit ordered set into two separate 64-bit chunks, applying error protection to each chunk independently. This segmentation allows CRC/parity protection to be applied more effectively to smaller data units, reducing the impact of bit errors and improving reliability without sacrificing the high-speed operation of the interconnect.
2Reliability
If CRC/parity protection is applied to each 64-bit chunk, then the bit error rate is reduced to 1.3E-10, but the device complexity increases
Solution Approach 1:
By dividing the ordered set into two 64-bit chunks, the patent applies error protection to smaller, more manageable units. This segmentation reduces the complexity of implementing and processing CRC/parity protection compared to applying it to the entire 128-bit ordered set as a single unit.
Solution Approach 2:
The patent applies error protection selectively to critical ordered sets (SKP OS and EIEOS) that require it, while using control payload flits for non-scrambled sets like EIOS. This partial application of error protection reduces overall system complexity while maintaining reliability where most needed.
3Reliability
If both 64-bit chunks must be correct for critical ordered sets, then the reliability is improved, but the loss of information increases when errors occur
Solution Approach 1:
The patent applies CRC/parity protection before the data transmission occurs, providing error detection and correction capabilities in advance. This beforehand cushioning allows the system to detect and handle errors gracefully, reducing information loss when errors do occur by enabling proper error recovery procedures.
Data Source
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AI summary
The disclosure comprises apparati, methods, storage medias and computer programs, which are configured to process ordered sets for identifying the appropriate Ordered Set, even in the presence of errors, and taking the appropriate action. The Ordered Set comprises a first eight bytes and a second eight bytes, wherein the five out of the first eight are checked whether the received Ordered Set matches a SKP OS, EIOS (300) or EIEOS. If Ordered Set is determined to be a SKP OS, determine at least five bytes of the second eight bytes to match a SKP_END OS and process a PHY payload that follows the matched SKP_END. If no match is found, cause a link, which received appropriate Ordered Set, to enter recovery.