Ordered Write Stash Streaming via Segmented Interconnect Routing
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Solution Overview
Problem
Current data processing systems struggle to efficiently stash strongly ordered write data into CPUs at high performance levels, especially in un-ordered interconnects, leading to sub-optimal performance and potential deadlocks.
Innovation Solution
The mechanism enhances the interconnect and transfer protocol to enable high-performance streaming of ordered write stashes by introducing optional COMP_ACK packet responses, WR_DATA_CANCEL data operations, and dual COMP_ACK flows, ensuring proper data ordering and handling of deadlocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If strongly ordered write stashes are handled by a system interconnect, then data ordering is maintained, but performance is degraded due to un-ordered interconnect routing
Solution Approach 1:
The patent segments the interconnect routing by introducing dedicated ordered stash routing paths separate from general un-ordered traffic. Write stashes are segmented into ordered and un-ordered categories, with ordered stashes routed through specialized paths that guarantee ordering while un-ordered traffic uses high-speed but non-guaranteed paths.
Solution Approach 2:
The patent introduces intermediary components including stash routing logic, completion tracking mechanisms, and acknowledgment management systems that mediate between the ordered write requirements and the un-ordered interconnect fabric. These intermediaries ensure ordering is maintained without bottlenecking the overall system.
2Productivity
If current interconnects stash strongly ordered write data into CPUs, then data is cached close to processing units, but deadlocks occur due to resource contention
Solution Approach 1:
The patent implements preliminary actions by pre-allocating resources and establishing routing paths before deadlocks can occur. Completion acknowledgments are tracked and managed in advance, and resource allocation is predetermined to prevent circular wait conditions that cause deadlocks.
Solution Approach 2:
The patent introduces feedback mechanisms including completion acknowledgments (COMP_ACK), data buffer credit messages (DBID_RSP), and deadlock detection logic. These feedback loops allow the system to monitor resource usage, detect potential deadlocks, and resolve them by canceling pending operations (WR_DATA_CANCEL) before they escalate into system-wide deadlocks.
3Productivity
If PCIe write bandwidth is increased to 32GBps, then I/O performance is improved, but existing interconnects cannot handle the bandwidth requirements
Solution Approach 1:
The patent adds dimensional complexity to the interconnect by introducing multiple routing dimensions including ordered/un-ordered paths, stash-specific routing, and completion tracking channels. This multi-dimensional approach allows the interconnect to handle high bandwidth by distributing traffic across multiple logical and physical paths rather than relying on a single high-capacity channel.
Solution Approach 2:
The patent changes key parameters of the interconnect including introducing new message types (WR_UNIQ_STASH, COMP_ACK, DBID_RSP, WR_DATA_CANCEL), adding routing priority levels, and implementing dynamic resource allocation. These parameter changes enable the interconnect to accommodate PCIe 4.0 bandwidth requirements while maintaining backward compatibility.
Data Source
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AI summary
A data processing network and method of operation thereof are provided for efficient transfer of ordered data from a Request Node to a target node. The Request Node send write requests to a Home Node and the Home Node responds to a first write request when resources have been allocated the Home Node. The Request Node then sends the data to the written. The Home Node also responds with a completion message when a coherency action has been performed at the Home Node. The Request Node acknowledges receipt of the completion message with a completion acknowledgement message that is not sent until completion messages have been received for all write requests older than the first write request for the ordered data, thereby maintaining data order. Following receipt of the completion acknowledgement for the first write request, the Home Node sends the data to be written to the target node.