Organic Chiplet Integration With Sub-1 μm Die-to-Die Routing
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Solution Overview
Problem
Current multi-die packaging technologies face challenges in achieving fine die-to-die interconnect routing due to limitations in die contact pad pitch, wiring line width/spacing, and pitch, which are constrained by traditional pick and place tools and via 0 diameter.
Innovation Solution
The implementation of advanced packaging techniques such as face down die placement, adaptive writing with adaptive lithography, and damascene processing, along with the use of photoimageable organic dielectric layers and inorganic barrier layers, enables the achievement of finer die contact pad pitch and higher wiring density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional pick and place tools are used for multi-die packaging, then ease of manufacture is maintained, but die contact pad pitch and wiring density cannot be reduced below certain limits
Solution Approach 1:
The patent replaces traditional mechanical pick and place tools with a carrier substrate-based system where dies are mounted on a carrier and then transferred as a unit. This substitution enables finer die contact pad pitch (3-5 μm) because the positioning precision is determined by the carrier substrate and reflow soldering process rather than mechanical tool limitations, while the overall process remains manageable through standardized carrier handling procedures
Solution Approach 2:
The patent performs preliminary mounting of multiple dies onto a carrier substrate before final package assembly. This preliminary action allows for precise positioning and soldering of dies to the carrier in a controlled manner, enabling fine pitch interconnections. The carrier serves as a temporary platform that facilitates high-precision die attachment, which would be difficult to achieve with direct pick and place to the final package
2Manufacturing precision
If via 0 diameter is reduced to increase wiring density, then wiring line width/spacing is improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent replaces mechanical drilling or punching methods for creating via 0 with a laser direct write process. This substitution enables wiring line widths and spacing of less than 1 μm because laser writing can create extremely fine features without mechanical tool limitations. The laser process directly writes the interconnect structures through the dielectric material, eliminating the need for traditional via formation steps and enabling higher wiring density while maintaining manufacturing feasibility
Solution Approach 2:
The patent changes the method of via 0 formation from mechanical to optical (laser), which fundamentally alters the achievable feature size parameters. The laser direct write process can create via 0 with diameters and wiring dimensions below 1 μm, whereas mechanical methods are limited by tool tip dimensions and positioning accuracy. This parameter change enables the required fine wiring density for high bandwidth applications
3Productivity
If die contact pad pitch is reduced to 3-5 μm to increase I/O density, then productivity and bandwidth are improved, but manufacturing precision requirements become extremely stringent
Solution Approach 1:
The patent replaces mechanical pick and place positioning with a carrier substrate system combined with reflow soldering. The carrier substrate provides a stable, precise platform for die mounting, and the reflow soldering process enables self-alignment of dies to the carrier pads. This substitution achieves 3-5 μm die contact pad pitch with high yield because the positioning precision is determined by the carrier fabrication process and soldering physics rather than mechanical tool limitations
Solution Approach 2:
The patent employs reflow soldering which enables self-alignment of dies to the carrier substrate through thermal expansion and capillary action. During reflow, the solder paste melts and creates strong metallurgical bonds that automatically pull the die into precise alignment with the carrier pads. This self-service alignment mechanism achieves the required 3-5 μm pitch precision without requiring extremely stringent external positioning controls
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These techniques allow for die contact pad pitches as low as 3-5 μm and wiring line widths/spacing of less than 1 μm, significantly increasing die contact pad and wiring density, thereby supporting high bandwidth applications with extremely high input/output (IO) requirements.
Implementation Method 1
The inorganic barrier layer may function as a stress barrier from the molding compound layer to a plurality of die-to-die interconnects in the package-level RDL connecting contact pads between each die
Implementation Method 2
The inorganic barrier layer may also shield wiring from mold pits (e.g. voids) in the molding compound layer
Implementation Method 3
photoimageable organic dielectric layers may facilitate conventional lithography techniques or adaptive writing and adaptive patterning to facilitate a higher contact pad density, as well as wiring density of the die-to-die interconnects
Implementation Method 4
Furthermore, damascene processing can be included at the package-level RDL to increase wiring density and the number of wiring layers
Data Source
AI summary
Structures and methods of forming fine die-to-die interconnect routing are described. In an embodiment, a package includes a package-level RDL than spans across a die set and includes a plurality of die-to-die interconnects connecting contact pads between each die. In an embodiment, the plurality of die-to-die interconnects is embedded within one or more photoimageable organic dielectric layers.