Organic Circuit Board Bridge Element for High-Density Interconnects
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Solution Overview
Problem
Existing circuit board technologies face high manufacturing costs and low yield due to the use of expensive silicon die interposers and wafer-level embedding methods, which are technically challenging and costly for achieving high-density chip-to-chip interconnections.
Innovation Solution
A circuit board structure featuring a cavity with a bridge element and solder resist lamination, where copper pillars are formed through electroplating to connect chip electrodes, eliminating the need for high-cost silicon die interposers and enabling fine-pitch interconnections using organic materials and traditional packaging technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon die interposer is used for chip-to-chip interconnection, then interconnection capability is improved, but manufacturing cost increases and production yield decreases
Solution Approach 1:
The patent replaces expensive silicon die interposers with a cost-effective organic substrate that serves the same interconnection function. The substrate uses conventional PCB materials and processes, eliminating the need for costly silicon wafer fabrication while achieving the required electrical and mechanical performance for chip-to-chip interconnection.
Solution Approach 2:
The patent changes the material parameter from silicon to organic substrate materials, and modifies the interconnection structure from TSV-based silicon vias to copper pillars formed by electroplating. This parameter change enables the use of standard PCB manufacturing processes instead of specialized silicon fabrication, significantly reducing cost and increasing yield.
2Reliability
If TSV with large aspect ratio is fabricated in silicon interposer, then electrical connection between chips is achieved, but fabrication difficulty and cost increase
Solution Approach 1:
The patent replaces complex TSV fabrication in silicon with a simpler copper pillar electroplating process on an organic substrate. This eliminates the need for high-aspect-ratio via drilling and plating in silicon, using instead conventional PCB lamination and electroplating techniques that are already standardized in the industry.
Solution Approach 2:
The patent substitutes the mechanical drilling and plating of high-aspect-ratio TSVs in silicon with a chemical electroplating process on copper-clad laminate. This replacement uses wet chemical processes instead of mechanical drilling, significantly reducing process complexity and equipment requirements.
3Area of moving object
If wafer-level embedding is used for chip mounting, then integration density is improved, but manufacturing cost increases and production flexibility decreases
Solution Approach 1:
The patent segments the chip mounting process into separate steps: first mounting chips on the organic substrate, then forming copper pillars, and finally completing interconnections. This segmentation allows for modular processing, enabling rework and inspection at intermediate stages, which improves yield compared to monolithic wafer-level embedding.
Solution Approach 2:
The patent performs preliminary chip mounting on the organic substrate before forming the copper pillars and completing interconnections. This preliminary action allows chips to be positioned and secured early in the process, enabling subsequent processing steps to proceed independently and improving overall production flexibility and yield.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and increases yield by using organic materials and standard packaging techniques, allowing for effective chip-to-chip interconnections without the need for expensive silicon die interposers, thereby improving integration density and minimizing signal loss.
Implementation Method 1
forming copper pillars in the first openings and in the second openings by electroplating
Data Source
AI summary
The present invention discloses a circuit board consisting of a cavity with predetermined depth in the substrate, a bridge element installed in said cavity for mounting a multiple of chips on the top surface of said bridge element, and a solder resist layer all over said bridge element and the outer layer of the substrate wherein the gap in between the bridge element and the cavity wall is filled with said solder resist lamination, wherein said bridge element comprises a wiring layer in a core of organic material for electrically connecting the electrodes on the top surface to those of the bottom surface, and wherein the copper pillar is formed through the openings in the solder resist over the electrode of the bridge element.