Organic-Substrate Die-to-Die Interconnect for Scalable Chiplet Packaging
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Solution Overview
Problem
Existing technologies face limitations in integrating multiple circuit elements on a silicon die due to communication constraints between chiplets, such as complex routing and power consumption issues with silicon interposers, and the size limitations of silicon interposers restrict the number of chiplets that can be integrated, leading to reduced system complexity and performance.
Innovation Solution
A physical layer interconnect using an organic substrate, such as a printed circuit board, to facilitate high-bandwidth communication between chiplets without the need for silicon interposers, allowing for longer trace lengths and greater chiplet integration on a package substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon interposers are used to couple multiple chiplets, then communication between chiplets is enabled, but the system complexity and manufacturing complexity increase due to complex routing and dense layout requirements
Solution Approach 1:
The patent uses an organic substrate as an intermediary carrier to replace the silicon interposer. This organic substrate provides a simplified platform for coupling multiple chiplets, reducing the routing complexity and manufacturing difficulty while maintaining the communication functionality between chiplets through trace-based interconnections.
Solution Approach 2:
The patent changes the material parameter from silicon to organic substrate, which fundamentally alters the manufacturing approach. Organic substrates allow for less dense routing patterns and simpler layout requirements compared to silicon interposers, thereby reducing device complexity while preserving communication capabilities.
2Power
If silicon interposers are used to integrate multiple chiplets, then communication bandwidth is provided, but power consumption increases
Solution Approach 1:
The organic substrate acts as a mediator that enables communication between chiplets with lower power consumption. The trace-based interconnection architecture on organic substrates reduces signal loss and interference compared to silicon interposers, thereby improving communication efficiency and reducing the energy required for data transmission.
3Reliability
If silicon interposers are used for chiplet integration, then communication between chiplets is achieved, but the size of the interposer limits the number of chiplets that can be integrated
Solution Approach 1:
The patent segments the integration platform into multiple organic substrate modules, each capable of carrying multiple chiplets. This modular approach allows for scalable integration of a larger number of chiplets without being constrained by the size limitations of a single silicon interposer, as additional organic substrate modules can be added to expand the system.
Solution Approach 2:
The organic substrate provides a universal platform that can accommodate various chiplet configurations and sizes. Unlike silicon interposers with fixed routing patterns, organic substrates offer flexible trace routing that can be adapted to different chiplet arrangements, enabling higher integration density and supporting a greater number of chiplets in diverse system configurations.
Data Source
AI summary
A physical layer interconnect between chips/chiplets provides high bandwidth communication with low power requirements using an organic substrate such as a printed circuit board. An interface between first and second chiplets uses a separate chiplet, or a combination logic die and interconnect interface, interfacing with the interconnect. A connection between a computing device and a memory can be longer, allowing the computing device to be coupled to more memories, expansion slots, or external connections. The interconnect can route memory commands between computing devices and memories, allowing multiple and different computing devices to be coupled to each other or to multiple and different memories. The memories can perform in-memory computing using chiplets coupled thereto. The interconnect couples to possibly different computing devices and possibly different memories, such as in a rack configuration, including CPUs or GPUs. The specialized processing devices can include one or more TPUs or VPUs.