Organic EL Pixel Wiring with Multilayer Lines for Initialization
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Solution Overview
Problem
Parasitic capacitance in signal lines of organic electro luminescence (EL) display devices leads to insufficient initialization of the gate terminal of drive transistors, potentially deteriorating image quality.
Innovation Solution
The display device incorporates a scanning line, initialization control line, light emission control line, and initialization voltage line connected to pixel circuits, with additional first and second connection lines formed in different layers, reducing parasitic capacitance and ensuring proper initialization of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal lines are connected to pixel circuits in a conventional manner, then the device structure is simple, but parasitic capacitance is generated causing insufficient initialization of the gate terminal
Solution Approach 1:
The patent introduces a multi-layer wiring structure where the scanning line and initialization control line are placed in different layers (first layer and second layer respectively). This spatial separation in the vertical dimension reduces parasitic capacitance between the lines while maintaining electrical connectivity through conductors, thereby improving initialization completeness without significantly increasing device complexity.
Solution Approach 2:
The patent introduces a dummy initialization control line as an intermediary element between the scanning line and the initialization control line. This dummy line acts as a mediator to equalize potential differences and reduce parasitic capacitance effects, ensuring proper initialization of the gate terminal while maintaining a relatively simple overall structure.
2Reliability
If the scanning line and initialization control line are connected directly, then the connection is simple, but image quality deteriorates due to parasitic capacitance effects
Solution Approach 1:
By separating the scanning line and initialization control line into different layers (first layer and second layer), the patent reduces parasitic capacitance between these lines. This spatial separation in the vertical dimension improves image quality by ensuring complete initialization while adding only moderate wiring complexity through the multi-layer configuration.
Solution Approach 2:
The patent divides the wiring structure into multiple segments across different layers. The scanning line is segmented into portions in the first layer, connected to the initialization control line in the second layer through conductors. This segmentation allows for reduced parasitic capacitance while maintaining functional connectivity, thereby improving image quality.
3Reliability
If conventional single-layer wiring is used, then manufacturing is easier, but parasitic capacitance causes insufficient transistor initialization
Solution Approach 1:
The patent transitions from a single-layer wiring structure to a multi-layer structure, placing the scanning line in the first layer and the initialization control line in the second layer. This vertical separation reduces parasitic capacitance and ensures proper transistor initialization. While multi-layer fabrication is slightly more complex, it remains compatible with standard thin-film transistor manufacturing processes.
Data Source
AI summary
The display device includes a plurality of pixel circuits, a scanning line, an initialization control line, a light emission control line, an initialization voltage line, a first connection line, and a second connection line. The first connection line and the second connection line connect the scanning line to the initialization control line connected to, of the plurality of pixel circuits, a pixel circuit different from a pixel circuit to which the scanning line is connected. Each of the plurality of pixel circuits includes a light-emitting element, a drive transistor, a light emission control transistor, a writing control transistor, and an initialization transistor. The first connection line and the second connection line are formed in layers different from each other.