Organic Interposer Barrier Layer for Thermal Stress Mitigation
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Solution Overview
Problem
The existing semiconductor packages with organic interposers face issues of warpage and cracking due to mismatched coefficients of thermal expansion between the interposer and the encapsulant, leading to reliability concerns and manufacturing challenges in achieving high bandwidth memory (HBM) integration.
Innovation Solution
A semiconductor package design that includes a stress barrier layer formed between the encapsulant and the semiconductor chip, using a material with a CTE greater than the chip but less than the encapsulant, to alleviate thermal expansion mismatch and enhance adhesion, thereby preventing warpage and cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a molding process is performed to maintain rigidity of the interposer package, then rigidity is improved, but warpage and cracking occur due to mismatch between coefficients of thermal expansion of the interposer and the encapsulant
Solution Approach 1:
A barrier layer is introduced as an intermediary component between the encapsulant and the semiconductor chip. This barrier layer has a coefficient of thermal expansion that is greater than that of the semiconductor chip but less than that of the encapsulant, serving as a thermal expansion buffer that reduces stress concentration and prevents warpage and cracking while maintaining package rigidity
Solution Approach 2:
The package structure employs composite material design by combining multiple materials with different coefficients of thermal expansion (semiconductor chip, barrier layer, encapsulant) in a layered configuration. This composite structure allows each material to contribute its optimal properties, achieving both rigidity and thermal expansion compatibility
2Ease of manufacture
If the coefficient of thermal expansion mismatch between interposer and encapsulant is not addressed, then manufacturing is simpler, but reliability deteriorates due to stress-induced defects
Solution Approach 1:
The barrier layer serves as a mediator that addresses the thermal expansion mismatch problem without significantly complicating the manufacturing process. It can be integrated into existing packaging workflows using standard deposition or lamination techniques, providing a reliable solution to stress-induced defects while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The barrier layer effectively reduces stress and prevents defects such as warpage and cracking, improving the reliability and manufacturing feasibility of the semiconductor package by maintaining package rigidity and ensuring proper thermal dissipation.
Implementation Method 1
mismatch between coefficients of thermal expansion (CTEs) of the interposer and the encapsulant of the die
Data Source
AI summary
A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed on side surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.