Organic Interposer Package Structure for High-Density Die Links
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Solution Overview
Problem
The increasing size of high-end and high-performance chips with multiple cores leads to decreased yields, prompting the need for advanced packaging solutions that enable high-bandwidth interconnection between dies while maintaining low production costs.
Innovation Solution
A package structure comprising a first package substrate with a low-density interconnection layer and a second package substrate with a high-density interconnection layer, where the second dielectric layer includes an organic material like polyimide, allowing for high-density interconnection without the need for traditional silicon processing equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If silicon interposer is used for high-density interconnection, then interconnection density is improved, but processing cost increases due to traditional silicon process requirements
Solution Approach 1:
The patent changes the material parameter of the interposer from silicon to organic material, which fundamentally alters the processing requirements. This parameter change enables the use of organic-based fabrication processes instead of traditional silicon processes, thereby reducing processing costs while maintaining high-density interconnection capabilities through the second package substrate
Solution Approach 2:
The patent employs a cost-effective organic material for the second package substrate that can be processed using inexpensive fabrication techniques. This approach replaces the expensive silicon interposer with a more economical alternative that achieves the same functional goal of high-density interconnection without requiring costly silicon processing equipment and environments
2Reliability
If silicon interposer with TSVs is used, then signal and power transmission is improved, but subsequent processing cost increases
Solution Approach 1:
The patent changes the material composition parameter from silicon dioxide-based dielectric to organic material-based dielectric. This parameter change eliminates the need for TSV formation and associated expensive subsequent processing steps, while still achieving reliable signal and power transmission through the organic material interposer structure
Solution Approach 2:
The patent extracts and eliminates the TSV formation step from the manufacturing process by using organic material that can be directly patterned and processed. This removes the need for complex back-surface via formation and subsequent expensive processing steps, while maintaining the essential function of signal and power transmission
3Power
If chip size is increased to accommodate more cores, then chip performance is improved, but yield decreases
Solution Approach 1:
The patent segments the interconnection function across multiple layers and substrates. The first package substrate provides initial interconnection, while the second package substrate with organic material provides high-density interconnection. This segmentation allows smaller individual chips to be interconnected effectively, maintaining high yield while achieving the performance of larger multi-core systems
Solution Approach 2:
The patent moves the interconnection density problem from the lateral plane to the vertical dimension by stacking multiple package substrates and interconnection layers. This dimensional transition enables high-density interconnection through vertical stacking rather than lateral expansion, allowing smaller chips to achieve high performance through three-dimensional integration
Data Source
AI summary
A package structure, a chip, an electronic apparatus, a manufacturing method for a package structure and a chip packaging method are provided. The package structure includes a first package substrate and at least one second package substrate, wherein the first package substrate includes a first interconnection layer, the first interconnection layer includes a first metal routing layer and a first dielectric layer which are alternately stacked, and the first interconnection layer is provided with at least one cavity; the second package substrate is arranged in the cavity and includes a second interconnection layer, wherein the second interconnection layer includes a second metal routing layer and a second dielectric layer which are alternately stacked, and the second dielectric layer includes an organic material; wherein a layout density of metal routings in the second metal routing layer is greater than a layout density of metal routings in the first metal routing layer.