Organic Substrate Interposer for High-Density Package Fabrication
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Solution Overview
Problem
Current semiconductor package technologies, such as through-silicon via (TSV) packages, face challenges in achieving miniature sizes and high density due to line width limitations, high costs, and reliability issues related to dielectric differences between substrates, leading to wasted circuit layout space and large blind hole openings.
Innovation Solution
A package substrate and fabrication method combining laser embedded (LE), thermal curing dielectric (TCD), and chemical mechanical polishing (CMP) processes to form interposers and internal circuits on the substrate, using an insulation layer with embedded circuit patterns as an interposer, replacing the silicon substrate in TSV technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through-silicon via (TSV) package technology is used to achieve high density and three dimensional integration, then the integration level increases beyond Moore's law, but the cost increases four times compared to FCBGA substrate
Solution Approach 1:
The patent changes the material parameter from silicon substrate to organic substrate, and changes the via formation method from TSV to blind hole etching. This allows achieving similar high-density interconnection functionality while reducing manufacturing cost by using less expensive organic substrates and simpler etching processes instead of expensive silicon-based TSV technology
Solution Approach 2:
The patent replaces expensive silicon substrates with cheaper organic substrates for the interposer layer. The organic substrate serves the same functional purpose of providing mechanical support and electrical interconnection but at a fraction of the cost, effectively using a cheaper alternative to achieve the same technical goal
2Ease of manufacture
If FCBGA package technology is used to reduce cost, then manufacturing cost decreases, but line width limitation prevents achieving L/S less than 65 μm and wastes circuit layout space
Solution Approach 1:
The patent introduces an organic substrate-based interposer as an intermediary layer between the chip and the PCB. This interposer serves as a mediator that enables fine-pitch interconnection (L/S < 65 μm) through its circuit patterns, while the overall package can still use cost-effective FCBGA technology for the bulk interconnection, thus resolving the contradiction between cost and precision
3Ease of manufacture
If blind hole openings in substrate are made larger to facilitate manufacturing, then ease of manufacture improves, but circuit layout space is wasted
Solution Approach 1:
The patent applies different opening sizes at different locations: smaller blind holes are used in areas where circuit layout space is needed, while larger openings are used only where necessary for via formation. The circuit patterns are strategically placed to utilize the available space efficiently, ensuring that the majority of the substrate area remains available for high-density circuit routing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables smaller package sizes with improved reliability, reduces processing time and cost, and addresses limitations in semi-additive processes, such as line width constraints and dielectric differences, while avoiding the need for large blind hole openings.
Implementation Method 1
A plurality of embedded bond pads are formed in a top surface of the insulation layer
Implementation Method 2
The insulation layer is cured
Implementation Method 3
chemical mechanical polishing (CMP) process
Data Source
AI summary
A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.