Organic Interposer Package Structure for Lower Signal and Power Loss
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Solution Overview
Problem
Conventional silicon-based interposers in semiconductor devices experience signal loss due to parasitic inductance and power loss, necessitating the development of an organic interposer with improved signal integrity (SI) and power integrity (PI) at a low cost and large area.
Innovation Solution
A semiconductor package incorporating an organic interposer with a stacked structure of multiple organic insulating layers, vias, and redistribution layers, connected via conductive metal materials, which reduces signal loss and power loss by enhancing electrical connections and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If silicon-based interposer is used, then electrical connection is achieved, but signal loss and power loss occur due to parasitic inductance
Solution Approach 1:
The patent changes the material parameter from silicon to organic substance, fundamentally altering the electrical characteristics to eliminate parasitic inductance. This material substitution transforms the interposer from having inductive properties to having resistive or capacitive properties, thereby reducing signal loss and improving signal integrity.
Solution Approach 2:
The patent employs composite material structures including organic insulating layers combined with conductive materials (such as copper or aluminum) for vias and traces. This composite approach allows the organic interposer to achieve both electrical connectivity and reduced parasitic effects by combining the advantages of different materials.
2Reliability
If organic interposer is used, then signal integrity and power integrity are improved, but manufacturing complexity increases
Solution Approach 1:
The organic interposer is divided into multiple functional layers including organic insulating layers, conductive layers, vias, and pads. This segmentation allows each layer to be optimized independently for its specific function while simplifying the overall manufacturing process through standardized layer-by-layer fabrication techniques.
Solution Approach 2:
The patent transitions from planar interposer designs to three-dimensional stacked structures with multiple organic insulating layers and vertical vias. This dimensional change enables improved signal integrity through better electrical isolation while maintaining manufacturability through established multi-layer PCB and semiconductor fabrication processes.
3Ease of manufacture
If large area interposer is used, then cost is reduced, but parasitic inductance increases causing signal loss
Solution Approach 1:
By changing the material parameter from silicon to organic substance, the patent enables large-area interposers to be manufactured at lower cost while simultaneously eliminating parasitic inductance. The organic material allows for larger fabrication areas without the same cost penalties as silicon, and its inherent electrical properties prevent signal loss even over larger distances.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The organic interposer effectively reduces internal signal loss and power loss, enabling improved performance in semiconductor packages while maintaining a low cost and large area, thereby addressing the limitations of silicon-based interposers.
Implementation Method 1
a plurality of first vias penetrating from the first organic insulating layer to the fourth organic insulating layer, and connecting first upper pads on an upper surface of the fourth organic insulating layer and lower pads on a lower surface of the first organic insulating layer
Implementation Method 2
a heat dissipation member on first upper surfaces and first upper portions of outer walls of the first semiconductor chip and on second upper surfaces and second upper portions of the second semiconductor chip
Data Source
AI summary
A semiconductor package includes a package substrate, an organic interposer on the package substrate, the organic interposer including a plurality of organic insulating layers including an organic compound, at least two semiconductor chips on the organic interposer, and a mold, on an upper surface of the organic interposer, surrounding the at least two semiconductor chips.