Organic Interposer Packaging Without TSVs for High-Density Interconnects

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Solution Overview

Problem

Traditional silicon-based interposer layers for 2.5D packaging are costly and difficult to control in terms of yield, limiting the efficiency of signal interconnection in high-density chip packaging.

Innovation Solution

A packaging structure with an organic interposer layer is developed, comprising a rewiring layer with metal and inorganic dielectric layers, conductive pillars, an organic dielectric layer, solder bumps, and bonding pads, which replaces traditional through-silicon vias to reduce manufacturing costs and improve yield control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional silicon-based interposer layers with TSV process are used, then signal interconnection can be achieved, but manufacturing cost increases and yield control becomes difficult

Engineering Contradiction:
Improvesignal interconnectionVSAvoidmanufacturing cost and yield control
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the material parameter of the interposer layer from silicon to organic material, and changes the interconnection structure parameter from TSV (through-silicon via) to through-organic-via (TOV). This material and structural parameter change enables simpler manufacturing processes, reduced costs, and improved yield control while maintaining signal interconnection functionality.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs organic interposer materials that are cheaper than silicon and can be processed more easily. The organic material allows for simpler via formation processes and is more forgiving during manufacturing, effectively replacing expensive silicon with a more economical alternative that achieves the same functional purpose.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Productivity

If high-density chip packaging is implemented, then more functional chips can be placed in smaller area, but manufacturing complexity increases

Engineering Contradiction:
Improvechip densityVSAvoidpackaging structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the packaging structure into distinct functional layers: organic interposer layer, through-organic-vias, metal wiring layers, and die attach structures. This segmentation allows each component to be optimized independently and simplifies the overall manufacturing process compared to traditional silicon-based heterogeneous integration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses composite material structures combining organic dielectric materials with metal wiring layers and conductive via fills. This composite approach enables high-density interconnection while maintaining manufacturability, as the organic matrix provides structural support and electrical isolation while metal components provide conductive pathways.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS20240063029A1Packaging structure having organic interposer layer and method for manufacturing same
Publication Date: 2024.02.22 SJ SEMICONDUCTOR (JIANGYIN) CORP
  • US20240063029A1 patent drawing
  • US20240063029A1 patent drawing
  • US20240063029A1 patent drawing

AI summary

A packaging structure having an organic interposer layer and a method for manufacturing the same are provided; the method comprises: forming a rewiring layer having metal wiring layers and inorganic dielectric layers over a semiconductor substrate; forming conductive pillars over the rewiring layer, and electrically connected to the rewiring layer; forming an organic dielectric layer over the rewiring layer, forming solder bumps over a thinned organic dielectric layer and thinned conductive pillars; bonding a support substrate to the solder bumps through an adhesive layer; removing the semiconductor substrate; forming bonding pads on an exposed surface of the metal wiring layers; connecting a cutting carrier to the bonding pads, and disengaging the support substrate by removing the adhesive layer. Interconnection between upper and lower layers is achieved by introducing the conductive pillars in the organic dielectric layer, without the need for complex processes such as forming through-silicon vias.