Un-cross-linked Organic Layer Planarization for Semiconductor Fabrication
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Solution Overview
Problem
Traditional semiconductor fabrication processes are inadequate in addressing wafer topography variations, leading to processing difficulties and device performance degradation due to increased complexity and reduced geometry sizes, which result in limited lithography and etching process windows.
Innovation Solution
A method involving a tri-layer or tetra-layer patterning scheme where an un-cross-linked organic layer is polished to planarize the surface, followed by a low-temperature film deposition without spin coating, and a photoresist layer formation, allowing for etching selectivity and reduced aspect ratios to mitigate topography variations and prevent solvent-induced damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional lithography methods are used, then the fabrication process is simple, but wafer topography variations cause limited process windows and reduced manufacturing precision
Solution Approach 1:
The patent applies preliminary action by performing a polishing process on the organic layer before subsequent lithography and etching steps. This pre-planarization of the wafer surface addresses topography variations in advance, creating a flatter surface that improves lithography process windows and manufacturing precision without requiring complex real-time adjustments during later fabrication steps.
2Strength
If the organic layer is thermally treated before polishing, then the material becomes cross-linked and harder, but this makes the polishing process more difficult and reduces ease of manufacture
Solution Approach 1:
The patent inverts the conventional sequence by polishing the organic layer while it is still in its soft, un-cross-linked state, rather than hardening it first. This reversal of the typical harden-then-polish approach allows for easier polishing with fewer process steps, improving ease of manufacture while still achieving the required surface planarity for subsequent lithography.
3Temperature
If spin coating is used for film deposition, then the film can be deposited at higher temperatures, but this causes solvent-induced damage and photoresist collapse
Solution Approach 1:
The patent changes the temperature parameter by depositing the film at low temperatures (below 100°C) rather than using conventional high-temperature spin coating. This parameter change prevents solvent-induced damage and photoresist collapse while still achieving uniform film deposition, thereby improving photoresist reliability without sacrificing deposition quality.
4Productivity
If geometry sizes are decreased to increase functional density, then more devices fit per chip area, but fabrication process tolerances are reduced and topography variations have greater impact
Solution Approach 1:
The patent applies preliminary planarization through polishing of the organic layer before lithography to reduce the impact of topography variations. This pre-treatment ensures that even as geometry sizes decrease and functional density increases, the fabrication process maintains adequate tolerances by starting with a flatter surface, thereby supporting continued scaling without proportionally reducing manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces wafer topography variations, prevents photoresist collapse, and integrates seamlessly into existing processes, enhancing fabrication precision and reducing costs by maintaining the organic layer's softness and avoiding thermal treatment-related issues.
Implementation Method 1
a polishing process is performed to the un-cross-linked material of the organic layer. The polishing process planarizes a surface of the organic layer.
Implementation Method 2
a film is deposited over the planarized surface of the organic layer
Data Source
AI summary
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of circuit devices over a substrate. The method includes forming an organic layer over the substrate. The organic layer is formed over the plurality of circuit devices. The method includes polishing the organic layer to planarize a surface of the organic layer. The organic layer is free of being thermally treated prior to the polishing. The organic material is un-cross-linked during the polishing. The method includes depositing a LT-film over the planarized surface of the organic layer. The depositing is performed at a temperature less than about 150 degrees Celsius. The depositing is also performed without using a spin coating process. The method includes forming a patterned photoresist layer over the LT-film.