Organic Interconnect MCM Layout for Scalable Memory-Logic Routing
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Solution Overview
Problem
Existing scalable systems face challenges in independently scaling logic and memory, leading to tradeoffs in parameters like bandwidth, capacity, power, latency, and footprint, which limits their performance and efficiency.
Innovation Solution
The implementation of multi-chip modules with routing substrates that include multiple metal routing layers, allowing for shorter die-to-die routing between adjacent dies and longer routing between farther apart dies, while also embedding I/O dies within the substrate to reduce logic die area and improve signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple logic dies are arranged side-by-side to support higher performance and memory capacity, then system scalability is improved, but the routing substrate wiring count increases and signal integrity deteriorates
Solution Approach 1:
The patent transitions from planar 2D routing to 3D vertical routing by stacking logic dies vertically and using through-silicon vias (TSVs) for inter-layer connections. This dimensional change allows routing signals to pass through the substrate vertically rather than horizontally across the entire substrate, dramatically reducing the wiring count on the routing substrate while maintaining scalability.
Solution Approach 2:
The patent embeds I/O dies within the routing substrate, nesting functional components inside the substrate structure itself. This nesting approach integrates I/O functionality directly into the substrate, reducing the need for external routing and simplifying the overall wiring architecture.
2Productivity
If higher data rates are used to improve bandwidth, then memory bandwidth is improved, but energy consumption increases and signal integrity deteriorates
Solution Approach 1:
By implementing vertical stacking with TSVs, the patent reduces the horizontal routing distance between logic and memory dies. This shorter interconnect length reduces signal attenuation and allows for lower data rates to achieve the same effective bandwidth, thereby reducing energy consumption while maintaining or improving bandwidth performance.
3Quantity of substance
If logic and memory are scaled together to increase system capacity, then memory capacity is improved, but the ability to independently tune compute and memory bandwidth is reduced
Solution Approach 1:
The patent segments the system into independently scalable logic die stacks and memory die stacks. Each stack can be configured with different numbers of dies and interconnect structures, allowing independent tuning of compute capacity and memory bandwidth. The modular stack architecture enables flexible configuration to meet specific system requirements without forcing coupled scaling.
4Device complexity
If I/O dies are integrated onto the logic die to reduce package complexity, then package complexity is reduced, but logic die area increases
Solution Approach 1:
The patent extracts I/O functionality from the logic die and places it in separate I/O dies that are embedded within the routing substrate. This extraction reduces the logic die area by removing I/O circuitry, while the I/O dies are positioned in the substrate where they can be efficiently connected to multiple logic dies through vertical routing, thereby reducing package complexity.
Data Source
AI summary
Multi-chip modules and methods of fabrication are described. The MCM may include a plurality of dies in which die-to-die routing can be partitioned within multiple metal routing layers for shorter die-to-die routings, while longer die-to-die routing can be routed primarily in a single metal routing layer. The plurality of dies may also be arranged in a spaced apart relationship to accommodate additional wiring area, while preserving direct routing areas for the longer die-to-die routing.