Conductive Organic Memory with Nanocrystal Barrier
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Solution Overview
Problem
Current memory devices, such as DRAM and flash memory, face challenges in power consumption, data retention, and integration due to their volatile nature and high voltage requirements, while non-volatile memory devices using conductive organic materials struggle with irregular threshold voltage and bistable conductive characteristics due to difficulties in forming nanocrystals with regular size and distribution.
Innovation Solution
A non-volatile memory device with a conductive organic material layer and a nanocrystal layer surrounded by an amorphous barrier, where the nanocrystals are formed using a plasma oxidation process, enabling stable threshold voltage and bistable conductive characteristics, allowing for multi-level data storage and high integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nanocrystals are formed in conductive organic material layer, then non-volatile memory characteristics are achieved, but nanocrystal size and distribution become irregular
Solution Approach 1:
An amorphous barrier layer is introduced as an intermediary between the substrate and the conductive organic material layer. This barrier layer serves as a template that guides nanocrystal formation, ensuring uniform size and distribution. The barrier layer mediates the interaction between the substrate and the organic material, enabling controlled nanocrystal growth while maintaining the desired electrical characteristics for non-volatile memory operation.
2Ease of manufacture
If conventional fabrication processes are used, then manufacturing is straightforward, but memory cell size is large and integration density is low
Solution Approach 1:
The invention transitions from planar two-dimensional memory cell layouts to a three-dimensional vertical stack architecture. Multiple memory cells are stacked vertically along the thickness direction, with each cell consisting of alternating layers of conductive organic material and amorphous barrier. This vertical stacking enables high integration density while maintaining compatibility with conventional fabrication processes, as the layered structure can be formed using standard deposition and patterning techniques.
3Reliability
If flash memory structure is used, then non-volatile storage is achieved, but high voltage is required and processing speed is slow
Solution Approach 1:
The invention changes the fundamental electrical parameters of the memory device by using conductive organic materials with distinct bistable conductive states instead of the charge trapping mechanisms in flash memory. The organic material layer exhibits high resistance and low resistance states that can be switched at low voltages, eliminating the need for high-voltage Fowler-Nordheim tunneling. This parameter change enables non-volatile storage with low power consumption and fast processing speeds comparable to volatile memory.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides stable data retention and high processing speed with a memory cell size of 4F2, achieving multi-level data storage and efficient integration by stabilizing nanocrystal size and distribution, thus overcoming the limitations of existing memory devices.
Implementation Method 1
the nanocrystals are formed using a plasma oxidation process
Implementation Method 2
the nanocrystals are formed using a plasma oxidation process
Data Source
AI summary
A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. The unit cell receives a plurality of voltage ranges to perform a plurality of operations. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range.