Organic Semiconductor Array Substrate for Low-Temperature Fabrication
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Solution Overview
Problem
The manufacturing of array substrates for display devices using plastic substrates is challenging due to low heat resistance and chemical resistance, leading to unreliable thin film transistors when forming semiconductor layers at temperatures below 200 degrees Celsius, and the use of amorphous silicon results in degraded semiconductor characteristics.
Innovation Solution
An array substrate with a thin film transistor featuring an organic semiconductor layer formed under lower temperatures, using a single gate electrode and specific passivation layers to prevent damage from patterning processes, reducing material costs and manufacturing time while maintaining semiconductor integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used to form semiconductor layers at temperatures below 200 degrees Celsius, then manufacturing cost is reduced, but semiconductor characteristics are degraded and reliability is poor
Solution Approach 1:
The patent changes the material parameter from amorphous silicon to organic semiconductor material, which enables formation at lower temperatures (below 200°C) while maintaining or improving semiconductor characteristics. This parameter change resolves the contradiction by finding a material that satisfies both low-cost manufacturing and high reliability requirements.
2Weight of moving object
If plastic substrates are used instead of glass substrates, then weight is reduced and flexibility is improved, but heat resistance and chemical resistance are insufficient leading to manufacturing difficulties
Solution Approach 1:
The patent changes the processing temperature parameter to be below 200°C, which matches the heat resistance capability of plastic substrates. This enables the use of lightweight plastic substrates while maintaining manufacturing reliability by ensuring all processing steps occur within the substrate's thermal tolerance.
3Reliability
If multiple gate electrodes and complex passivation layers are used to protect organic semiconductor layers, then semiconductor integrity is maintained, but device complexity and manufacturing time increase
Solution Approach 1:
The patent merges the gate electrode structure into a single integrated component that provides both electrical function and protective coverage. The gate electrode is designed to extend over the organic semiconductor layer, combining the functions of electrical control and physical protection, thereby reducing the need for separate complex passivation structures.
Solution Approach 2:
The gate electrode is designed to serve multiple functions: electrical control of the transistor and physical protection of the organic semiconductor layer during patterning processes. This multi-functionality reduces the overall device complexity by eliminating the need for separate protective structures.
4Device complexity
If organic semiconductor layers are formed without protective structures, then manufacturing process is simplified, but the layers are damaged during patterning processes
Solution Approach 1:
The gate electrode is designed to extend over the organic semiconductor layer, merging the electrical control function with the protective function. This integrated structure protects the semiconductor layer during patterning while maintaining process simplicity, resolving the contradiction between complexity and precision.
Data Source
AI summary
A fabricating method of an array substrate includes forming source and drain electrodes in each of pixel regions on a substrate; forming an organic semiconductor layer and a gate insulating layer on the source and drain electrodes, the organic semiconductor layer having an island shape and contacting facing ends of the source and drain electrodes, the gate insulating layer having a same plane shape as the organic semiconductor layer; forming a first passivation layer on the gate insulating layer; forming a gate electrode on the first passivation layer in the pixel region, the gate electrode corresponding to the gate insulating layer; forming a second passivation layer on the gate electrode, the second passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer, the pixel electrode contacting the drain electrode through the drain contact hole.