ORing FET Circuit for Negative Current Blocking and Low Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing ORing FETs operate in either linear or saturation modes, leading to inefficiencies in power transmission due to high drain-source resistance at heavy loads and high negative current backflow at no/light loads, respectively.
Innovation Solution
An ORing circuit with an ORing FET operating in a nonlinear mode, where the drain-source resistance is low at heavy loads and high at no/light loads, controlled by a comparing circuit to limit negative current and protect output voltage, using transistors and resistances to manage gate-source voltage and drain-source resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ORing FET operates in linear mode, then the gate-source voltage remains at threshold level at no load, but the drain-source resistance remains high causing low power transmission efficiency
Solution Approach 1:
The patent applies dynamics by transitioning the ORing FET from static operation modes (linear or saturation) to dynamic nonlinear mode operation. The FET's drain-source resistance is dynamically adjusted based on operating conditions: at no load, the resistance increases to block negative current, while at heavy load, the resistance decreases to improve power transmission efficiency. This dynamic adaptation resolves the contradiction between negative current blocking and power transmission efficiency.
2Loss of energy
If the ORing FET operates in saturation mode, then the gate-source voltage remains at maximum value, but the drain-source resistance remains low causing high negative current backflow at no load
Solution Approach 1:
The patent uses dynamic operation to switch the FET between different resistance states based on load conditions. In nonlinear mode, the FET automatically adjusts its drain-source resistance: maintaining low resistance during heavy load for efficient power transmission, and increasing resistance at no load to block negative current backflow. This dynamic behavior eliminates the need to choose between the two static modes and resolves the contradiction.
3Loss of energy
If the ORing FET operates in nonlinear mode, then the drain-source resistance adapts to load conditions, but the circuit complexity increases due to additional control components
Solution Approach 1:
The patent implements self-service by designing a control circuit that automatically adjusts the ORing FET's gate-source voltage based on the load current without requiring external intervention. The control circuit monitors the operating conditions and autonomously transitions the FET between linear and saturation modes, achieving adaptive nonlinear operation. This self-regulating mechanism reduces the need for complex external control systems while maintaining power transmission efficiency and negative current blocking capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nonlinear mode ORing FET achieves high efficiency in power transmission by minimizing negative current backflow and maintaining output voltage regulation, combining the advantages of linear and saturation modes while preventing current reversal.
Implementation Method 1
The ORing FET operates in a nonlinear mode. When the output current loading is at heavy load, the drain-source resistance of the ORing FET is low, which causes high efficiency on power transmission. When the output current loading is at no/light load, the drain-source resistance of the ORing FET is high, which causes low negative current flowing back to the ORing FET.
Data Source
AI summary
An ORing circuit is provided. The ORing circuit includes an input port, an output port, an ORing FET, a comparing circuit, a first transistor and a second transistor. The ORing FET is connected between the input port and the output port and comprises a source connected with the input port, a gate and a drain connected with the output port. The comparing circuit is connected with the input port and the gate. The first transistor comprises a first terminal, a second terminal and a third terminal. The first terminal is connected with the input port and the source, and the third terminal is connected with the gate. The second transistor comprises a fourth terminal, a fifth terminal and a sixth terminal. The fourth terminal is connected with the output port and the drain, and the sixth terminal is connected with the second terminal of the first transistor.