Orthogonally Stacked RAM Cell Structure for Density and Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices face challenges in achieving high integration and data retention time, with SRAM requiring more transistors for high capacity leading to increased area and DRAM needing frequent refresh operations.
Innovation Solution
A random access memory with a 4T0C structure featuring orthogonally stacked transistors, eliminating the need for separate capacitors and allowing for a more compact design, which includes a read transistor and a write transistor in different layers, enabling faster operations and improved data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM uses at least six transistors per memory cell to achieve high-speed operation, then operation speed is improved, but integration density deteriorates due to increased area
Solution Approach 1:
The patent transitions from planar 2D transistor arrangement to 3D vertical stacking, where transistors are stacked in multiple layers along the vertical dimension. This allows six transistors to be arranged in a compact vertical configuration rather than spreading out horizontally, thereby maintaining high-speed SRAM operation while dramatically reducing the memory cell footprint and improving integration density.
2Area of stationary object
If DRAM uses 1T1C cell structure to achieve high integration, then integration density is improved, but data retention time deteriorates and frequent refresh is required
Solution Approach 1:
The patent employs vertical stacking of transistors in multiple layers to create a 3D memory cell structure. This vertical architecture enables the implementation of six-transistor SRAM cells with enhanced retention characteristics compared to conventional planar DRAM, achieving both high integration density and extended data retention time without requiring frequent refresh operations.
3Adaptability or versatility
If conventional memory cells use 6T structure for BNN application, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent implements a vertical stacked transistor architecture where six transistors are arranged in multiple vertical layers. This 3D configuration maintains the necessary 6T structure for binary neural network (BNN) operations and XNOR functionality while reducing planar complexity and improving manufacturability compared to conventional planar 6T cell designs.
Data Source
AI summary
A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor disposed on a same plane as the first transistor and including a second gate extending in the first direction, a third transistor including a third gate extending in a second direction perpendicular to the first direction and formed on the first transistor, a fourth transistor including a fourth gate extending in the second direction and formed on the second transistor, a first storage node connecting the first gate of the first transistor to a drain of the third transistor and storing data, and a second storage node connecting the second gate of the second transistor to a drain of the fourth transistor and storing data.