Orthogonal Compute Brick Stacking for High-Bandwidth Die Packaging
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Solution Overview
Problem
Current Multi-Chip Module (MCM) packaging architectures are limited in scaling to higher bandwidth and signal speeds due to bandwidth reduction, signal delay, and signal distortion, primarily because IC dies are stacked parallel to each other, which restricts the placement of high-power compute IC dies and hinders efficient heat dissipation.
Innovation Solution
The proposed solution involves coupling IC dies with orthogonal surfaces using interconnects that form oxide-oxide and metal-metal bonds, allowing for a metallization stack with conductive traces orthogonal to one surface and parallel to another, enabling vertical stacking and improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If IC dies are stacked parallel to each other in traditional MCM packaging, then the packaging structure is simple and easy to manufacture, but the bandwidth is reduced and signal speed is limited
Solution Approach 1:
The patent transitions from traditional parallel stacking (2D arrangement) to vertical stacking (3D arrangement) of IC dies. The compute dies are stacked vertically along the Z-axis with orthogonal surfaces facing each other, enabling higher density and improved bandwidth while maintaining manufacturing feasibility through standardized vertical interconnect processes.
2Ease of manufacture
If IC dies are stacked parallel to each other in traditional MCM packaging, then the manufacturing process is straightforward, but signal delay and signal distortion increase
Solution Approach 1:
By stacking compute dies vertically with orthogonal surfaces, the patent shortens the signal path length between dies compared to parallel stacking. This vertical arrangement reduces signal delay and distortion while the standardized interconnect structure maintains manufacturing simplicity.
3Device complexity
If high-power compute IC dies are placed in traditional parallel stacking, then the structure remains simple, but heat dissipation becomes inefficient
Solution Approach 1:
The vertical stacking architecture separates high-power compute dies from memory dies along the vertical axis, enabling dedicated heat dissipation paths. Heat can be dissipated vertically through thermal interfaces and heat sinks without interfering with other components, improving thermal management while maintaining structural organization.
Solution Approach 2:
The patent applies different thermal management strategies to different regions: compute dies with high power density are positioned with optimized thermal interfaces, while memory dies have different thermal requirements. This localized thermal management approach improves overall heat dissipation efficiency.
4Adaptability or versatility
If traditional parallel stacking is used, then the placement of high-power compute IC dies is restricted, but the density of compute dies cannot be increased
Solution Approach 1:
Vertical stacking along the Z-axis dramatically increases compute die density compared to parallel stacking in the XY-plane. Multiple compute dies can be stacked vertically with orthogonal surfaces, enabling higher density while maintaining placement flexibility through standardized vertical interconnect interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the ability to scale MCMs to higher bandwidths and signal speeds by allowing for more efficient heat dissipation and increased density of high-power compute IC dies, addressing the limitations of traditional parallel stacking.
Implementation Method 1
coupling IC dies with orthogonal surfaces using interconnects that form oxide-oxide and metal-metal bonds
Implementation Method 2
coupling IC dies with orthogonal surfaces using interconnects that form oxide-oxide and metal-metal bonds
Implementation Method 3
enhances the ability to scale MCMs to higher bandwidths and signal speeds by allowing for more efficient heat dissipation
Data Source
AI summary
Embodiments of a microelectronic assembly comprise: a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die, and a second plurality of IC dies coupled to at least the first IC die or the second IC die. Each IC die in the first plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective first planar interface, each of the first IC die and the second IC die includes a respective substrate and a respective metallization stack attached along a respective second planar interface, each IC die in the second plurality of IC dies includes a respective substrate and a respective metallization stack attached along a respective third planar interface, and the first planar interface is orthogonal to the second planar interface.