Orthogonal Die Stack Layout With Redistribution Layers for Power Delivery
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Solution Overview
Problem
Conventional IC die stacking architectures face limitations in power delivery and heat removal as stacks grow taller, limiting the number of high-power compute IC dies that can be placed within a constrained footprint.
Innovation Solution
The dies in the stack are positioned orthogonal to the base, with each die connected directly to the base via a redistribution layer, allowing direct power and input/output communication, and incorporating a redistribution layer on each die face to enhance electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional IC die stacking architectures are used with dies stacked parallel to the base, then the structure is simple and easy to manufacture, but power delivery and heat removal become inefficient as stacks grow taller
Solution Approach 1:
The patent transitions from conventional parallel stacking to orthogonal stacking where dies are positioned perpendicular to the base die. This dimensional change allows direct connection between each die in the stack and the base die through redistribution layers, enabling efficient power delivery and heat removal while maintaining manufacturing feasibility through adapted fabrication processes
2Productivity
If the number of high-power compute IC dies is increased within a constrained footprint, then processing power increases, but power delivery and heat removal become more difficult
Solution Approach 1:
By stacking dies orthogonally to the base die rather than parallel, the patent enables direct vertical connections from each die to the base die's power and ground networks. This allows higher-density integration of compute dies while maintaining efficient power delivery through shortened current paths and improved heat removal through direct thermal coupling to the base die heat spreader
Solution Approach 2:
The patent divides the interconnection architecture into modular redistribution layers on each die face, allowing independent power delivery and signal routing to each die in the stack. This segmentation enables scalable integration of multiple high-power compute dies without compromising power delivery efficiency
3Device complexity
If conventional parallel die stacking is used, then fewer redistribution layers are needed, but data transfer rates and power consumption are suboptimal
Solution Approach 1:
The orthogonal stacking configuration with redistribution layers on each die face enables direct vertical signal paths between dies and the base die, significantly reducing signal propagation delay and increasing data transfer rates. The additional redistribution layer complexity is offset by the elimination of long horizontal interconnect paths through other dies
Data Source
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AI summary
Microelectronic assembly architectures including a die stack in which each die includes a redistribution layer, and the die stack is positioned such that the face of each die is perpendicular to a face of a base, are provided. Each die has a first face and a second face opposite the first face, and an edge extending between the first and second faces. A redistribution layer is deposited on the first face of each die. The faces of each die in the die stack are parallel to the faces of the other dies. The die stack is positioned on the base such that the faces of each die are orthogonal to the face of the base. Each die can have a conductive contact on a bottom edge, and the conductive contact can be coupled to the respective redistribution layer on the die and to a conductive contact on the base.