Orthogonal IC Die Stacking for High-Bandwidth MCM Packaging
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Solution Overview
Problem
Current Multi-Chip Module (MCM) packaging architectures are limited in scaling to higher bandwidth and data speeds due to signal delay, loss, and distortion, primarily because IC dies are stacked parallel to each other, which restricts the placement of high-power compute IC dies and limits the package's ability to dissipate heat effectively.
Innovation Solution
The proposed solution involves coupling IC dies with orthogonal surfaces using interconnects that include dielectric-dielectric bonds and metal-metal bonds, allowing for a metallization stack with conductive traces parallel to one surface and orthogonal to the other, enabling vertical stacking and improved thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If IC dies are stacked parallel to each other in traditional MCM packaging, then the package structure is simple and easy to manufacture, but the bandwidth and data speed are limited due to signal delay, loss, and distortion
Solution Approach 1:
The patent transitions from traditional parallel stacking of IC dies to a vertical stacking architecture where dies are arranged in multiple tiers along the vertical dimension. This dimensional change enables shorter signal paths between dies, reducing signal delay and allowing higher bandwidth and data speeds while managing heat dissipation through the vertical arrangement
2Power
If high-power compute IC dies are placed in traditional parallel stacking, then computing power is increased, but heat dissipation becomes difficult and thermal management is compromised
Solution Approach 1:
By arranging IC dies in vertical tiers rather than parallel layers, the patent creates additional thermal pathways through the vertical dimension. Heat can be dissipated from multiple surfaces of the stacked dies, improving thermal management capability while maintaining high computing power from multiple high-power compute IC dies
Solution Approach 2:
The patent divides the package into multiple tiers with intermediate substrates, creating segmented thermal zones. Each tier can be independently managed for heat dissipation, allowing high-power compute IC dies to be placed in configurations that optimize both computing power and thermal management
3Quantity of substance
If vertical stacking of IC dies is implemented, then density of high-power compute IC dies is increased and thermal management is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent divides the vertical stack into multiple tiers, each containing a subset of IC dies mounted on intermediate substrates. This segmentation allows for modular manufacturing where each tier can be assembled and tested independently before final integration, reducing the complexity of manufacturing the entire vertical stack in one process
Solution Approach 2:
The patent introduces intermediate substrates as mediators between tiers of IC dies. These intermediate substrates provide mechanical support, electrical interconnections, and thermal management interfaces, enabling the vertical stacking architecture to be manufactured using adapted versions of existing packaging processes rather than requiring entirely new manufacturing methods
Data Source
AI summary
Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.