Orthogonal LDPC Base Graph for Lower-Complexity Parallel Decoding

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing Low-Density-Parity-Check (LDPC) coding systems, particularly those using quasi-cyclic (QC) parity-check matrices, require significant hardware resources for encoding and decoding, leading to inefficiencies and increased complexity.

Innovation Solution

The implementation of rate-adaptive LDPC codes with orthogonal base graphs and punctured information columns in the extension part of the parity check matrix, reducing conflicts and enabling simpler hardware implementation by processing adjacent rows in parallel, thus improving throughput and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If quasi-cyclic (QC) parity-check matrices are used for LDPC coding, then code performance and error correction capability are improved, but hardware resources and system complexity increase significantly

Engineering Contradiction:
Improveerror correction capabilityVSAvoidhardware resources
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parity-check matrix is divided into a base graph that can be systematically extended to generate codes of different rates. This segmentation allows the same base structure to serve multiple coding rates without redesigning the entire matrix, reducing hardware resources while maintaining error correction capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the structural parameters of the parity-check matrix by enforcing orthogonality constraints on adjacent rows in the extension part. This parameter change enables more efficient hardware implementation by reducing conflicts and allowing parallel processing, thereby lowering device complexity while preserving reliability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If QC LDPC encoding and recovery algorithms are implemented, then data protection and transmission reliability are enhanced, but processing time and computational overhead increase

Engineering Contradiction:
Improvedata protectionVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The base graph structure segments the encoding and decoding processes into modular operations that can be executed in parallel. By organizing the parity-check matrix into a base graph with orthogonal extension parts, the algorithms can process different sections simultaneously, reducing processing time while maintaining data protection.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The base graph is pre-designed with orthogonal properties that eliminate conflicts before processing begins. This preliminary structural arrangement allows the encoding and recovery algorithms to proceed without computational conflicts, reducing processing time and overhead while maintaining enhanced data protection.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If adjacent rows in the extension part of the base PCM are made orthogonal, then hardware implementation complexity is reduced and parallel processing is enabled, but code design constraints increase

Engineering Contradiction:
Improvehardware implementationVSAvoidcode design flexibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The base graph with orthogonal extension parts serves as a universal structure that can generate LDPC codes of multiple rates through systematic extension. This multi-functional design reduces hardware implementation complexity while maintaining code design flexibility, as the same base structure adapts to different coding requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10879927B2Compact low density parity check (LDPC) base graph
Publication Date: 2020.12.29 FUTUREWEI TECHNOLOGIES INC
  • US10879927B2 patent drawing
  • US10879927B2 patent drawing
  • US10879927B2 patent drawing

AI summary

A decoding method, an encoding method, a decoder and an encoder are disclosed. In an embodiment the decoding method includes receiving, at a receiver of a receiving side, signals from a transmitting side, the signals including a code word and decoding, at a decoder of the receiving side, the code word using a low density parity check (LDPC) code in which each n adjacent rows, n>1, in an extension part of a base parity check matrix (PCM) are orthogonal except for punctured information columns.