Self-aligned via formation using orthogonal mandrel layers
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Solution Overview
Problem
The formation of vias in semiconductor devices using staggered configurations on non-orthogonal arrays is challenging, especially as feature sizes decrease, due to difficulties in imaging and achieving high-fidelity shapes at diagonal or non-orthogonal angles with traditional mask making processes.
Innovation Solution
A method involving the use of mandrels and non-mandrel materials with self-aligned double pattern techniques, where orthogonal mandrel layers are formed over a hard mask, allowing for the creation of vias at non-orthogonal angles by etching and planarizing to achieve smaller critical dimensions and precise pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional mask making processes are used to form vias on non-orthogonal arrays, then the process is simple and straightforward, but imaging becomes challenging and manufacturing precision deteriorates as feature sizes become smaller
Solution Approach 1:
The patent divides the pattern formation process into multiple discrete steps: forming first and second mandrel layers with different orientations, depositing spacer material, and performing selective etching. This segmentation allows each step to be optimized independently, achieving high precision via formation on non-orthogonal arrays while managing process complexity through systematic breakdown of the fabrication sequence
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional self-aligned double patterning by forming mandrels in different orientations (first layer and second layer) and using vertical spacer deposition. This dimensional approach enables precise via placement on non-orthogonal arrays by utilizing spatial relationships in multiple dimensions rather than relying solely on planar mask alignment
2Length of moving object
If feature sizes are reduced to achieve smaller critical dimensions, then via size decreases enabling higher density interconnects, but imaging difficulty increases and pattern fidelity deteriorates
Solution Approach 1:
The patent employs self-aligned double patterning where the first and second mandrel layers automatically define the positions of subsequent features through their spatial relationships. The spacer material self-aligns to the mandrels, and the etch process self-limits at the hard mask layer, eliminating the need for additional alignment steps and maintaining pattern fidelity even as critical dimensions decrease to enable higher density via formation
Solution Approach 2:
The patent performs preliminary pattern formation by depositing the hard mask layer and forming the first mandrel layer before creating the second mandrel layer. This preliminary action establishes a foundation that guides subsequent patterning steps, ensuring that even as feature sizes are reduced, the pre-established structural framework maintains imaging precision and pattern fidelity throughout the fabrication process
Data Source
AI summary
A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.