Orthogonal Riser Card Layout for PCIe Airflow and Cooling
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Solution Overview
Problem
Conventional computing systems face challenges with midplanes that block airflow and reduce thermal performance due to increased trace counts and higher power dissipation as they transition to higher speed buses like PCIe Gen 5, requiring more complex and costly designs that hinder cooling efficiency.
Innovation Solution
The implementation of vertically oriented riser cards with electrical traces and orthogonal connectors allows for improved airflow and reduced complexity by aligning I/O modules and power supply units in parallel, using a housing assembly with a fan assembly and canister design that facilitates easy alignment and disconnection, ensuring efficient airflow and thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional midplanes are used to support higher speed buses like PCIe Gen 5, then I/O pin count and signal quality are improved, but device complexity and manufacturing cost increase due to higher layer count construction
Solution Approach 1:
The patent divides the traditional single midplane structure into multiple separate riser cards, each handling specific I/O connections. This segmentation allows each riser card to have fewer layers and simpler construction while collectively providing the required high pin count for PCIe Gen 5 and higher speed protocols.
Solution Approach 2:
The patent transitions from a planar midplane layout to a three-dimensional arrangement with vertically oriented riser cards. This dimensional change enables better airflow paths and thermal management while accommodating high pin count requirements through spatial optimization rather than increasing layer count.
2Speed
If more traces are added to support higher speed buses, then signal quality and bandwidth are improved, but power dissipation increases and thermal performance deteriorates
Solution Approach 1:
By segmenting the trace paths across multiple separate riser cards rather than concentrating all high-speed traces on a single midplane, the patent reduces power dissipation density in any one location. Each riser card handles a subset of the total I/O traffic, distributing thermal load more effectively.
Solution Approach 2:
The vertical orientation of riser cards creates three-dimensional trace routing that improves airflow around and between signal paths. This spatial arrangement enhances heat dissipation efficiency while maintaining the required trace counts for high-speed protocols.
3Speed
If conventional midplanes are used with increased trace counts, then support for higher speed protocols is achieved, but airflow is blocked and thermal performance is reduced
Solution Approach 1:
The patent replaces the solid midplane structure with multiple spaced-apart riser cards, creating vertical airflow channels between them. This segmented approach maintains all necessary electrical connections while allowing unrestricted airflow from front to rear of the housing assembly, directly addressing thermal management requirements.
Solution Approach 2:
The arrangement of vertically oriented riser cards with spaces between them creates a porous-like structure that permits airflow penetration. This configuration allows cooling air to pass through the I/O region efficiently, preventing hot spots and maintaining thermal performance in high-speed protocol environments.
Data Source
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AI summary
A computing system (60) including a housing assembly having a front and a rear, a CPU module (12) positioned towards the front of the housing assembly and including a plurality of I/O connectors (78), and a plurality of I/O modules (32) positioned towards the rear of the housing assembly, where each I/O module (32) includes a second I/O connector (40). The computing system also includes a plurality of riser cards (76) each having a PCB (84) with opposing side surfaces, a front edge, a rear edge, a top edge, a bottom edge, a third I/O connector (86) coupled to the bottom edge and a fourth I/O connector (90) coupled to the rear edge. The third I/O connector (86) on each riser card (76) is connected to one of the first I/O connectors (78) and the fourth I/O connector (90) on each riser card (76) is connected to one of the second I/O connectors (40) so that the riser cards (76) are oriented in parallel with each other so as to define spaces therebetween relative to a front to rear direction of the housing assembly.