Orthogonal Multi-Phase Scheduling Circuitry for IC Bandwidth
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Solution Overview
Problem
Conventional command schedulers in integrated circuits face challenges in meeting timing constraints and managing complexity, area, and power consumption when trying to utilize the full interface bandwidth by sending multiple commands per internal clock cycle, often resulting in performance penalties in bandwidth and latency.
Innovation Solution
The implementation of orthogonal multi-phase scheduling circuitry, which partitions the command scheduler into multiple independent scheduling circuits, each handling a subset of commands and operating at different phases of the internal clock cycle, allowing for increased bandwidth and reduced latency while simplifying the circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple commands are sent per internal clock cycle to utilize full interface bandwidth, then interface bandwidth utilization is improved, but device complexity and scheduling complexity increase substantially
Solution Approach 1:
The command scheduler is segmented into multiple independent scheduling circuits, where each circuit handles a specific subset of commands or a specific phase. This segmentation reduces the complexity of each individual scheduling circuit while collectively achieving multi-command issuance per internal clock cycle, thereby resolving the contradiction between bandwidth utilization and device complexity.
2Productivity
If multiple commands are sent per internal clock cycle to increase bandwidth, then command bus bandwidth is improved, but area consumption increases dramatically
Solution Approach 1:
By dividing the scheduler into multiple independent circuits that operate in parallel or at different phases, the total area is distributed across these circuits. Each circuit is simpler and smaller than a single monolithic multi-command scheduler, achieving the same bandwidth utilization with reduced overall area consumption.
3Productivity
If multiple commands are sent per internal clock cycle to improve bandwidth, then interface throughput is improved, but power consumption increases dramatically
Solution Approach 1:
The segmentation into multiple independent scheduling circuits allows for selective activation and independent power management. Each circuit can be powered down or put into low-power mode when not needed, reducing overall power consumption compared to a single always-active complex scheduler, while still achieving high throughput through coordinated operation.
4Device complexity
If only one command is sent per internal clock cycle to meet area and power budgets, then device complexity is reduced, but bandwidth and latency performance suffer substantial penalties
Solution Approach 1:
The segmentation approach enables the system to achieve multi-command issuance capability through multiple simple circuits rather than one complex circuit. This maintains manageable device complexity while significantly improving bandwidth and latency performance by utilizing the interface more efficiently.
Solution Approach 2:
The scheduling circuits operate at different phases of the internal clock cycle, issuing commands periodically at different time points. This phased periodic action allows multiple commands to be issued per internal clock cycle while keeping each individual circuit simple, thereby improving performance without substantially increasing complexity.
Data Source
AI summary
An integrated circuit may include orthogonal multi-phase scheduling circuitry. The scheduling circuitry may include a number of orthogonal scheduling circuits each of which is configured to receive different command types and to output a single winning command. The scheduling circuitry may further include a phase assignment circuit for receiving the winning commands from the orthogonal scheduling circuits and for assigning the received winning commands to different corresponding phase groups. Each orthogonal scheduling circuit may include command buffers, command arbiters, a global arbiter, and associated safe checking circuits.