Orthogonal Signal Processing Architecture for Parallel QR Decomposition
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Solution Overview
Problem
Existing signal processing technologies, particularly those based on century-old mathematical principles, fail to maximize processing parallelism and reduce processing latency, which is crucial for advanced applications like 6G technology and MIMO systems.
Innovation Solution
A novel orthogonalization-driven methodology using a Symmetric Orthogonalization Cell (SOC) building block unit and N-inputs-with-2N-outputs architecture, which includes a multi-cylindrical parallel processing architecture to identify and locate mutually orthogonal q-vectors, reducing hardware redundancy and enhancing computational symmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional signal processing algorithms based on century-old mathematical principles are used, then computational correctness is maintained, but processing parallelism is not maximized and processing latency is high
Solution Approach 1:
The patent segments the signal processing task into multiple independent parallel operations by decomposing the input vector processing into N independent SOC chains, where each chain processes a different permutation of the input vectors. This segmentation enables maximum processing parallelism while maintaining computational correctness of the QR decomposition algorithm.
Solution Approach 2:
The patent transitions from traditional sequential processing to a multi-dimensional parallel architecture by organizing SOCs in N independent chains that simultaneously process different permutations. This dimensional expansion from 1D sequential to ND parallel processing maximizes throughput and minimizes latency for signal processing tasks.
2Productivity
If N independent chains of SOCs are used to process all permutations, then processing parallelism is maximized, but device complexity increases
Solution Approach 1:
The patent makes each SOC universal by designing it to handle any pair of input vectors through permutation processing. Each SOC chain can process any permutation of the N input vectors, making the architecture multi-functional and adaptable to different signal processing scenarios while maintaining a standardized building block design.
Solution Approach 2:
The patent manages complexity by parameterizing the architecture with N (number of inputs) and using configurable permutation processing. The system adapts to different problem sizes by changing the parameter N rather than redesigning the entire architecture, allowing scalable complexity management while maintaining maximum parallelism.
3Productivity
If traditional N-inputs-with-N-outputs architecture is used, then hardware utilization is standard, but processing parallelism and computational symmetry are not fully exploited
Solution Approach 1:
The patent intentionally introduces asymmetry in the architecture design by using N independent chains with different permutation assignments rather than a symmetric N-inputs-N-outputs structure. This asymmetric design allows each chain to specialize in specific permutations, fully exploiting computational symmetry in the underlying math while achieving maximum processing parallelism.
Data Source
AI summary
Disclosed is a novel orthogonalization-driven and architecturally comprehensive methodology, including computer-implemented methods and modular architectures, that can significantly enhance processing parallelism and reduce processing latency for a wide spectrum of computationally intensive signal processing tasks. This methodology also plays a crucial role in the design of high-performance integrated circuit chips for these tasks. Developing the overall methodology requires using an unique N-inputs-with-2N-outputs processing structure as the baseline architecture.