Orthogonal Underlayer Dummyfill for Overlay Target Metrology
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Solution Overview
Problem
Current overlay metrology targets face issues such as dishing, etch bias, parasitic capacitance, lithographic incompatibility, and increased metrology footprint due to design rule violations and pattern density incompatibilities, leading to process damage and metrology biases.
Innovation Solution
The design incorporates orthogonal underlayer dummyfill patterns in overlay targets, which include segmented inactive pattern elements disposed orthogonally to overlay pattern elements, formed from separate process layers on a substrate, enhancing process compatibility and allowing for twofold or fourfold rotational symmetry for improved manufacturing and metrology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If overlay targets are printed with device layers on a wafer, then overlay measurements can be performed, but dishing occurs within or in the vicinity of the target due to chemical mechanical polishing
Solution Approach 1:
The patent introduces an intermediary dummy fill layer between the overlay target and the underlying structure. This dummy fill layer acts as a buffer that absorbs the mechanical stress and material removal during chemical mechanical polishing, preventing the dishing effect from propagating to the overlay target structures and maintaining measurement precision.
2Ease of manufacture
If pattern elements are made smaller to improve process compatibility, then manufacturing compatibility improves, but etch bias increases due to incompatible pattern density
Solution Approach 1:
The patent changes the density parameter of the pattern elements by introducing dummy fill structures. This adjusts the overall pattern density to be compatible with etch process requirements, ensuring uniform etch rates and minimizing etch bias while maintaining the ability to perform accurate overlay measurements.
3Area of stationary object
If design rules are violated to achieve compact target structures, then device footprint is reduced, but parasitic capacitance increases in manufactured devices
Solution Approach 1:
The patent extracts the dummy fill structures from the active device areas and places them in dedicated regions surrounding the overlay target. This separation removes the parasitic capacitance-generating elements from the critical device paths while maintaining their function in providing proper pattern density and process compatibility for the target structures.
4Measurement precision
If target size is increased to improve measurement accuracy, then metrology precision improves, but reticle and wafer footprint increases excessively
Solution Approach 1:
The patent segments the overlay target into multiple smaller measurement regions or sub-targets that can be measured independently. This segmentation allows for high measurement precision to be achieved through multiple localized measurements rather than requiring a single large target, thereby reducing the overall reticle and wafer footprint while maintaining metrology accuracy.
Data Source
AI summary
The disclosure is directed to designing and using an overlay target with orthogonal underlayer dummyfill. According to various embodiments, an overlay target may include one or more segmented overlay pattern elements forming at least one overlay target structure. The overlay target may further include one or more inactive pattern elements forming at least one dummyfill target structure. Each of the one or more inactive pattern elements may include dummyfill segmented along an axis orthogonal to a segmentation axis of at least one proximately disposed overlay pattern element. In some embodiments, each of the target structures or layers may be formed from a separate process layer successively disposed upon a substrate, such as a silicon wafer. In some embodiments, the overlay and dummyfill target structures may be twofold or fourfold rotationally symmetric to allow for certain manufacturing or metrology advantages.