Stacked Semiconductor Power Routing With Orthogonal Supply Lines
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face challenges in achieving higher degrees of integration due to power supply voltage drops and noise, which are exacerbated by finer processes, and existing solutions do not adequately address the structure of power supply lines in stacked semiconductor chips or the supply of power to buried interconnects.
Innovation Solution
A novel structure for power supply lines is introduced, where the first semiconductor chip with transistors is connected to the second semiconductor chip through vias, allowing for low-resistance power supply lines without the need for additional power supply lines in the first chip, and enabling different wiring pitches and processes for each chip, thus facilitating cost-effective fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply lines are thickened to reduce resistance and prevent power supply voltage drop and noise, then power supply quality is improved, but wiring region for signal lines is blocked, resulting in reduced integration degree
Solution Approach 1:
The patent transitions from planar power supply lines to three-dimensional vertical power supply paths using TSVs (Through-Silicon Vias). Power is supplied from the second chip's power supply lines, through TSVs to the first chip's power supply lines, and then to the transistors. This vertical dimension allows sufficient power delivery without blocking signal line regions in the horizontal plane, resolving the contradiction between power supply quality and integration density.
2Reliability
If power supply lines are thickened to reduce resistance, then power supply voltage drop is reduced, but device complexity increases due to additional wiring layers
Solution Approach 1:
The patent extracts the power supply function from the first chip's wiring structure and relocates it to the second chip. The second chip's power supply lines and TSVs form a dedicated power delivery system, separating power supply functionality from signal processing functionality. This reduces the first chip's wiring complexity while maintaining low-resistance power paths.
3Manufacturing precision
If the same fabrication process is used for both stacked chips, then manufacturing consistency is improved, but fabrication cost increases due to process limitations
Solution Approach 1:
The patent segments the fabrication process into independent stages for the first chip and second chip. Each chip can be fabricated using optimized processes suitable for its specific function, then stacked and connected via TSVs. This segmentation allows the use of mature, cost-effective processes for each chip type without requiring complex multi-chip simultaneous fabrication, reducing overall manufacturing costs while maintaining quality.
Data Source
AI summary
A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.