Orthotopic Pattern Metrology for Intralayer Alignment
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Solution Overview
Problem
Conventional methods for intralayer alignment in semiconductor wafer fabrication rely on critical dimension metrology, which can fail to detect misalignments due to differences in line slope and pitch, leading to faulty devices if not addressed.
Innovation Solution
An orthotopic pattern metrology system that uses a scanning electron microscope and computing system to analyze the relationship between lines, measuring both line-independent and line-interdependent features to determine correct placement and generate instructions for alignment adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional critical dimension metrology is used to measure line width and line-edge roughness, then the measurement process is simple and fast, but it fails to detect misalignments due to differences in line slope and pitch
Solution Approach 1:
The patent segments the pattern measurement into multiple independent features: line width, line-edge roughness, line slope, and pitch. By measuring each feature separately and then综合分析, the system achieves comprehensive alignment detection without requiring a completely new metrology approach. The segmentation allows existing CD-SEM capabilities to be extended with additional measurement dimensions.
Solution Approach 2:
The patent transitions from two-dimensional critical dimension measurement (line width and edge roughness) to three-dimensional pattern characterization by adding line slope and pitch measurements. This dimensional expansion enables detection of misalignments that conventional two-dimensional metrology cannot detect, while building upon existing measurement infrastructure.
2Manufacturing precision
If only line width and line-edge roughness are measured, then the measurement process is quick and straightforward, but misalignments in line placement are not detected
Solution Approach 1:
The patent performs preliminary measurements of line slope and pitch alongside critical dimension measurements in a single scanning process. By collecting all necessary data during the initial scan rather than requiring separate measurement steps, the system minimizes additional time investment while ensuring comprehensive pattern verification before pattern transfer.
Solution Approach 2:
The system implements feedback by comparing measured line slope and pitch values against expected values, generating alerts when misalignments are detected. This feedback mechanism enables real-time detection and correction of placement errors, improving manufacturing precision without requiring extensive rework or multiple measurement passes.
3Measurement precision
If comprehensive pattern analysis including line relationships is performed, then alignment accuracy is improved, but the complexity of the measurement and analysis process increases
Solution Approach 1:
The patent segments the complex pattern analysis into distinct measurement components: individual line critical dimensions, individual line slope measurements, and pitch measurements between adjacent lines. This segmentation simplifies the overall analysis complexity by breaking down the comprehensive pattern characterization into manageable, independent measurement tasks that can be processed systematically.
Solution Approach 2:
The patent creates a universal measurement framework that uses the same basic scanning and measurement techniques for all pattern features (line width, slope, pitch). By applying a multi-functional approach where a single measurement system performs multiple types of measurements using consistent methods, the system reduces analysis complexity while achieving comprehensive pattern verification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves the accuracy of intralayer alignment by considering the relationship between lines, reducing the likelihood of faulty devices and enhancing the precision of pattern placement on semiconductor wafers.
Implementation Method 1
A conventional CD-SEM uses an electron beam to form images of microscopic features of a patterned wafer at extremely high magnification
Data Source
AI summary
Described herein are technologies to facilitate the fabrication of substrates, such as semiconductor wafers. More particularly, technologies described herein facilitate the correct placement of patterns of lines and spaces on a substrate. The resulting patterned substrate is the product of photolithography process and/or the pattern transference (e.g., etching) that occurs during the fabrication of substrates (e.g., semiconductor wafers). The scope of the present invention is pointed out in the appending claims.