OS-FeFET Structure With High-k Buffer for Stable Synaptic Switching
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Solution Overview
Problem
The von Neumann architecture in computers is limited by memory access speed, which is slower than processing speed, making it inefficient for neural network operations that require large data movement, and consumes significant energy.
Innovation Solution
Development of an oxide semiconductor ferroelectric field effect transistor (OS-FeFET) that integrates memory and processing units, utilizing a ferroelectric layer to simulate synaptic behaviors and reduce interface trap generation, compatible with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If von Neumann architecture is used with separate memory and processing units, then device complexity is reduced and manufacturing is easier, but memory access speed becomes the bottleneck and energy consumption increases
Solution Approach 1:
The patent merges memory and processing units into a unified neuromorphic computing system where artificial neurons and artificial synapses are integrated on the same substrate. This eliminates the von Neumann bottleneck by allowing processing to occur directly where data is stored, thereby improving memory access speed and reducing energy consumption associated with data movement between separate memory and processing units.
Solution Approach 2:
The oxide semiconductor ferroelectric field effect transistor serves multiple functions simultaneously: it acts as both a memory element (through ferroelectric polarization states) and a processing element (through synaptic weight modulation). This multi-functionality allows the same device to perform both storage and computation, further improving speed and reducing energy consumption by eliminating redundant data transfer operations.
2Reliability
If ferroelectric layer is used to simulate synaptic behaviors, then neuromorphic computing performance is improved, but interface trap generation increases causing threshold voltage shifts
Solution Approach 1:
The patent introduces a high-k dielectric layer as an intermediary between the ferroelectric layer and the oxide semiconductor channel. This intermediate layer acts as a buffer that reduces direct interaction and charge trapping at the ferroelectric-semiconductor interface, thereby minimizing interface trap generation and threshold voltage shifts while preserving the symmetrical synaptic characteristics provided by the ferroelectric layer.
Solution Approach 2:
The patent employs a composite structure combining ferroelectric material (for synaptic behavior), high-k dielectric material (for interface protection and electric field management), and oxide semiconductor material (for stable channel formation). This composite material approach leverages the strengths of each material while mitigating their individual weaknesses, achieving both reliable synaptic characteristics and stable threshold voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The OS-FeFET provides symmetrical potentiation/depression synaptic characteristics, enhancing neuromorphic computing performance by reducing threshold voltage shifts and energy consumption.
Implementation Method 1
a ferroelectric layer over the electrode and the first dielectric layer
Implementation Method 2
The high-k dielectric layer is configured to modify the Fowler-Nordheim (FN) tunneling behavior between the ferroelectric layer and the oxide semiconductor layer
Data Source
AI summary
Oxide semiconductor ferroelectric field effect transistors (OS-FeFETs) and method of forming the same are provide. A device disclosed herein includes an electrode in a first dielectric layer, a ferroelectric layer over the electrode and the first dielectric layer, a high-k dielectric layer over the ferroelectric layer, an oxide semiconductor layer over the high-k dielectric layer, a second dielectric layer over the oxide semiconductor layer and the high-k dielectric layer, and a first contact feature and a second contact feature extending through the second dielectric layer to contact the oxide semiconductor layer.