Operating System Memory Error Interception for BMC Monitoring

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Solution Overview

Problem

Current methods fail to effectively monitor and detect memory downgrade errors out-of-band when the SMI is disabled after EMCA2 is enabled, leading to unrecorded key errors and increased inconvenience in diagnosing system issues.

Innovation Solution

The method involves intercepting and parsing memory errors by the operating system, sending a memory downgrade error log to the BMC, and using an algorithm to detect and locate uncorrectable memory inspection errors, by setting correctable machine check interrupts and processing errors through the CMCI, thereby avoiding SMI storms and enabling out-of-band monitoring.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If SMI is disabled after EMCA2 is enabled to avoid SMI storms, then system stability is improved, but memory downgrade errors cannot be detected out-of-band

Engineering Contradiction:
Improvesystem stabilityVSAvoidmemory downgrade error detection
Core Design Contradiction:
Stability of the object's compositionVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces an intermediary mechanism where the operating system acts as a mediator between the memory error detection function and the out-of-band system. When SMI is disabled, the OS intercepts memory error signals through CMCI, processes them, and forwards relevant error information to the BMC, enabling indirect error detection without triggering SMI storms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the direct SMI-based error notification mechanism with an OS-based software handling mechanism. Instead of using hardware interrupts (SMI) to notify the system of memory errors, the OS uses software-based error interception and processing, substituting the mechanical interrupt system with a software layer that can filter and forward errors appropriately.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Difficulty of detecting and measuring

If SMI is triggered for error processing to enable out-of-band error detection, then error monitoring capability is improved, but SMI storms cause machine downtime

Engineering Contradiction:
Improveerror monitoring capabilityVSAvoidmachine downtime
Core Design Contradiction:
Difficulty of detecting and measuringVSLoss of time

Solution Approach 1:

The patent applies partial action by selectively triggering error processing only when necessary. Instead of continuously monitoring and triggering SMI for every memory error, the system uses OS-based interception to process errors selectively, triggering SMI only when needed and filtering out redundant error signals to prevent SMI storms.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent implements a feedback mechanism where the OS continuously monitors memory error conditions, processes them, and provides feedback to the BMC through log files. This feedback loop enables the out-of-band system to receive error information without requiring continuous SMI interrupts, allowing the system to respond to errors asynchronously.

Inventive Principle:
Principle #23Feedback

3Productivity

If error threshold is set to trigger SMI for processing, then error processing is activated, but key errors are covered by next correctable errors resulting in reporting failure

Engineering Contradiction:
Improveerror processing activationVSAvoiderror reporting accuracy
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent applies preliminary action by having the OS intercept and process memory error signals before they can be covered by subsequent correctable errors. The OS continuously monitors error conditions and records error information in advance, ensuring that even transient or covered errors are captured and reported to the BMC before the error state changes.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11853150B2Method and device for detecting memory downgrade error
Publication Date: 2023.12.26 INSPUR SUZHOU INTELLIGENT TECH CO LTD
  • US11853150B2 patent drawing
  • US11853150B2 patent drawing

AI summary

A method and device for detecting a memory downgrade error. The method comprises: capturing and analyzing a memory error by means of an operating system (OS); sending a memory downgrade error log to a management chip BMC on a server motherboard according to the analysis result; and after the BMC receives log information, detecting and locating an uncorrectable memory inspection error on the basis of an algorithm.