OS Scheduler for Multi-Core Performance Scaling

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Solution Overview

Problem

Current operating system schedulers fail to scale effectively with a high number of processor cores, as they do not adapt to dynamic application needs and lead to inefficiencies in power management, limiting performance gains in multi-core systems.

Innovation Solution

A space-shared scheduling approach that dynamically adjusts the frequency of processor cores based on application requests, allowing for near-linear scaling of performance with the number of cores, and improves cache usage by not relying on thread migration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If current symmetric multi-processing scheduling is used, then system stability is maintained, but performance scaling to hundreds or thousands of cores is limited by Amdahl's law

Engineering Contradiction:
Improveperformance scalingVSAvoidscheduling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the monolithic scheduler into hierarchical levels: a global scheduler managing core groups and a local scheduler managing individual cores within each group. This segmentation allows the system to scale to hundreds or thousands of cores while maintaining manageable complexity at each scheduling level, overcoming the limitation of current symmetric multi-processing approaches.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension to scheduling by organizing cores into hierarchical groups rather than flat individual management. This dimensional change from one-level to two-level scheduling enables the system to handle large numbers of cores efficiently, achieving performance scaling beyond what traditional approaches can deliver.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If frequency is increased to improve processing speed, then performance increases, but power consumption and cooling requirements increase

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic frequency adjustment where the operating frequency of processor cores is adapted based on actual workload demands. The system can scale frequency dynamically rather than maintaining high frequency continuously, thus achieving high processing speed when needed while reducing power consumption during lower workload periods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operating frequency parameter of processor cores dynamically according to application requirements. By adjusting this physical parameter rather than maintaining a fixed high frequency, the system achieves high processing speed when necessary while significantly reducing power consumption and cooling requirements during normal operation.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If thread migration is used to balance load, then resource utilization improves, but cache usage characteristics deteriorate

Engineering Contradiction:
Improveresource utilizationVSAvoidcache performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent extracts the load balancing function from thread migration and implements it at the core group level instead. The global scheduler balances workload across core groups while the local scheduler manages threads within each group, eliminating the need for frequent thread migration between cores. This preserves cache performance by keeping threads on the same core while still achieving resource utilization through core group balancing.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP2435914B1Method and scheduler in an operating system
Publication Date: 2019.12.11 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • EP2435914B1 patent drawingFigure 1
  • EP2435914B1 patent drawingFigure 2
  • EP2435914B1 patent drawingFigure 3

AI summary

Method and scheduler in an operating system, for scheduling processing resources on a multi-core chip. The multi-core chip comprises a plurality of processor cores. The operating system is configured to schedule processing resources to an application to be executed on the multi-core chip. The method comprises allocating a plurality of processor cores to the application. Also, the method comprises switching off another processor core allocated to the application, not executing the sequential portion of the application, when a sequential portion of the application is executing on only one processor core. In addition, the method comprises increasing the frequency of the one processor core executing the application to the second frequency, such that the processing speed is increased more than predicted by Amdahl's law.