OS Deactivation of Storage Block Write Protection
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Solution Overview
Problem
In computing environments, the process of changing write protection for storage blocks requires a quiescing operation that involves broadcasting and serialization among all processors, leading to increased time and resource usage, especially with multiple processors, which hampers performance during frequent memory management operations like copy-on-write and change-tracking.
Innovation Solution
A computer program product that includes instructions for an operating system to receive an address translation protection exception interrupt and determine if write protection is active, allowing it to clear or modify translation lookaside buffer entries without waiting for other processors, thereby avoiding the need for a quiescing operation and reducing suspension of instruction processing and contention for serialization mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a quiescing operation is performed to ensure system-wide consistency when changing write protection, then reliability is improved, but productivity deteriorates due to suspension of instruction processing and increased time requirements
Solution Approach 1:
The patent segments the write protection change operation into two independent parts: (1) the initiating processor clears its local TLB entries immediately, and (2) other processors are notified asynchronously to clear their own TLB entries when convenient. This segmentation allows the initiating processor to proceed without waiting for other processors, eliminating the quiescing operation while maintaining consistency through individual processor responsibility.
Solution Approach 2:
The patent applies preliminary action by having the initiating processor clear its own translation lookaside buffer (TLB) entries before notifying other processors. This preliminary local action ensures that the initiating processor immediately reflects the write protection change, while other processors are given flexibility to clear their TLB entries at their convenience without blocking the overall operation.
2Measurement precision
If a quiescing operation is performed to synchronize all processors, then measurement precision of write protection state is improved, but loss of time increases due to serialization requirements
Solution Approach 1:
The initiating processor performs preliminary action by clearing its own TLB entries immediately when write protection is deactivated. This ensures the processor has accurate information about the write protection state without waiting for other processors to synchronize, eliminating the time-consuming quiescing operation while maintaining measurement precision through local action.
Solution Approach 2:
Instead of requiring all processors to synchronize (excessive action), the patent allows each processor to clear its own TLB entries independently at its own pace (partial action). The initiating processor takes the necessary action immediately, while other processors perform the action partially and asynchronously, reducing the overall time loss without compromising the accuracy of write protection state visibility for each processor.
3Reliability
If system-wide broadcasting is performed to notify all processors of write protection changes, then reliability of permission synchronization is improved, but device complexity increases due to serialization mechanisms
Solution Approach 1:
The patent segments the notification process into independent processor-specific actions. Instead of a centralized broadcasting mechanism that requires all processors to stop and synchronize, each processor independently clears its own TLB entries when it receives notification or determines the write protection state has changed. This segmentation eliminates the need for complex serialization mechanisms while maintaining reliable permission synchronization through distributed independent action.
Solution Approach 2:
Each processor serves itself by independently clearing its own translation lookaside buffer entries when write protection changes occur. The initiating processor clears its own TLB entries, and other processors clear theirs when they become aware of the change. This self-service approach eliminates the need for complex system-wide broadcasting and serialization mechanisms, reducing device complexity while maintaining reliable permission synchronization through autonomous processor behavior.
Data Source
AI summary
Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.